Sony Corporation

Katsuyuki Kato

Hiroyuki Miwa

Takayuki Gomi

Takashi Noguchi

Hirokazu Ejiri

Shigeru Kanematsu

Hiroaki Anmo

Norikazu Ouchi

Hiroaki Ammo

A high-resistance polycrystalline Si resistor having a stable resistance value even when micro-sized and a low-resistance polycrystalline Si resistor having a sufficiently low desired resistance value wherein a polycrystalline Si film is formed on an insulation film located on a Si substrate, high-resistance-making ion implantation is applied to the entire surface and medium-resistance-making ion implantation is selectively applied to a medium-resistance-making region of the polycrystalline Si film. Low-resistance-making ion implantation is selectively applied to a low-resistance-making region of the polycrystalline Si film. The product is annealed to grow the polycrystalline Si film by solid-phase growth, the film is patterned to form a high-resistance polycrystalline Si resistor, medium-resistance polycrystalline Si resistor, and low-resistance polycrystalline Si resistor.

Method of manufacturing semiconductor resistors

Semiconductor device and its manufacturing method

A semiconductor device and a manufacturing method therefor which can simultaneously realize both a reduction in base transit time by a reduction in base width and a reduction in base resistance by a reduction in link base resistance. The semiconductor device is manufactured by the method including the steps of forming a first impurity diffused layer of a first conduction type in a semiconductor substrate; forming a conducting film connected to the first impurity diffused layer; forming a first insulating film on the conducting film; forming a first hole through a laminated film composed of the first insulating film and the conducting film; forming a second impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the first hole; forming a side wall from a second insulating film in the first hole to form a second hole; and forming a third impurity diffused layer of the first conduction type in the semiconductor substrate exposed to the second hole.

Manufacturing method for making bipolar device having double polysilicon

A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.

Method of making an SOI transistor

A method of manufacturing semiconductor interconnection includes the steps of providing a bottom conductive layer having an auxiliary conductive layer applied on top of the bottom conductive layer. The auxiliary conductive layer is patterned and subsequently a further conductive layer is applied over the patterned auxiliary conductive layer. A mask is then applied over the further conductive layer to form a pillar connection which provides a reliable connection in a semiconductor device.

Process of making a semiconductor device with a multilayer wiring and

Manufacturing method for making bipolar device

Method and apparatus for SOI transistor

Method of making SOI Transistor

A semiconductor device of a multilayer wiring structure provided with a bottom conductive layer and a top conductive layer connected through a pillar connection portion, wherein the bottom conductive layer has a pattern determined by the sum of the pattern of the auxiliary conductive layer formed on the bottom conductive layer and the pattern of the pillar connection portion. Also, a process for production of a semiconductor device including a step of forming a bottom conductive layer, a step of forming an auxiliary conductive layer on the bottom conductive layer, a step of patterning just the auxiliary conductive layer to obtain a first pattern of the auxiliary conductive layer, a step of forming a pillar conductive layer on the bottom conductive layer, a step of patterning the pillar conductive layer by a predetermined second pattern to obtain a second pattern of a pillar connection portion, and a step of etching the bottom conductive layer with etching masks of the second pattern of the pillar connection portion and the first pattern of the auxiliary conductive layer to pattern the bottom conductive layer by a pattern determined by the sum of the first pattern and the second pattern.

Semiconductor device wiring structure

Method for making bipolar transistor having double polysilicon structure

Growing community of inventors

Kanagawa, Japan

Katsuyuki Kato