Matsushita Electric Industrial Co., Ltd.

Katsuyuki Kaneko

Masaru Uya

Hiroshi Kadota

Hiroshi Tsutsui

Ichiro Okabayashi

Yoshito Nishimichi

Yoshiteru Mino

Nobufusa Iwanishi

Toshiyoshi Yamamoto

Koji Zaiki

Yuji Tanikawa

Yasuhiko Shinkaji

Yoshimasa Obayashi

Takayoshi Yuzu

Shinichi Nakahara

Yoshiteru Il

Yukio Hyouga

Sadafumi Tomida

Satoshi Gokita

The present invention provides a method of preventing or reducing X-ray-induced temporal changes of a semiconductor photoelectric conversion film formed on a TFT substrate, in which a protective film or sheet is used to protect the semiconductor photoelectric conversion film in order to improve weather resistance such as light blocking effect and moisture resistance. The present invention provides a radiation detecting element characterized by including a substrate having a plurality of pixel areas formed thereon, each having at least one switching element and at least one charge storage capacity, a photoelectric conversion film formed on the individual pixel areas for converting radiation into electrical charge, a protective film individually covering the photoelectric conversion film and having an area that is substantially the same as or larger than that of at least the photoelectric conversion film and a seal member and a sealant arranged so as to enclose the photoelectric conversion film, for fixing the protective film.

Radiation detecting element and method of manufacturing the same

In order to prevent destruction of a read gate by excessive storage of charge without any addition or change to the manufacturing process, the array type X-ray detection apparatus using a direct conversion system, which directly converts irradiation X-rays to charge, provides each pixel cell with a sensor section for converting X-rays to an amount of charge according to the amount of X-rays, a charge collecting electrode for storing the charge generated, a read gate for transferring the stored charge to an external read amplifier and a MIS diode using a TFT. A clamp signal is applied to one end of the MIS diode. The read gate and MIS diode are formed in the same manufacturing process. Since the amount of charge stored in the charge collecting electrode is clamped to the amount of charge corresponding to the clamp signal voltage by the MIS diode, the read gate is not destroyed even with excessive X-ray irradiation. Furthermore, instead of the MIS diode, a cutoff voltage control circuit and a cutoff gate using a TFT connected to the cutoff voltage control circuit are provided. When the output of the charge storage capacitor exceeds a cutoff voltage, the cutoff gate interrupts the inflow of charge to the charge storage capacitor to suppress further increase of output, thus preventing the read gate from being destroyed.

Array type X-ray detection apparatus

A compiling method comprises the steps of analyzing the characters and phrases in the source code of a program, analyzing the syntax of the program, and analyzing the meaning of the program, a program division step of dividing the program into a plurality of processes, a data reference analysis step of analyzing the data reference relations among the individual processes obtained through the division of the program and extracting first data used only in one process of the program and second data the value of which need not be preserved in some processes of the program, a memory area allocation step of allocating the memory area for the above first data to another data in any process in which the above first data is not used and allocating the memory area for the above second data to another data in some processes in which the value of the above second data need not be preserved, and the step of generating and outputting the object code of the program.

System for allocating the memory area of second data which value need

One block of non-zero coefficients obtained through the decoding of the entropy decoding unit 2024 is stored in the coefficient storage unit 121 in accordance with positional coordinates calculated by the non-zero coefficient scanning order calculation unit 2023a and the non-zero coefficient position conversion unit 2023b. The stored non-zero coefficients are then inverse quantized by the inverse quantization unit 2022. The non-zero coefficient range calculation unit 122 specifies a region of the coefficient storage unit 121 in which the non-zero coefficients are stored. The calculation order control unit 123 controls the inverse DCT unit 2021 to only perform an inverse DCT (discrete cosine transform) for non-zero coefficients located in the specified region.

Apparatus for decompressing image data which has been compressed using a

A data transfer apparatus for providing efficient data transfer between one memory device and multiple devices by providing high speed switching of the multiple devices according to a count of the number of the data transfers performed between the one memory device and any of the multiple devices. The data transfer apparatus comprises a transferring unit for controlling a data transfer between the memory and a device; a counting unit for counting one each time data is transferred; and a selecting unit for selecting a device in accordance with a count value by decoding the count value output from the counting unit. The transferring unit controls the data transfer between the memory and the device selected by the selecting unit. The above data transfer apparatus may include the counting unit consisting of n-bits of a binary counter, 2.sup.n devices, and the selecting unit consisting of a decoder that inputs n-bits and outputs 2.sup.n -bits of data.

Data transfer apparatus and system providing high speed switching to

In each processing device of a parallel processor system, a processor outputs a signal when all the transmit data are transmitted to a router. A latch receives the signal from the processor to output a signal set to HIGH. To an AND gate are inputted the signal set to HIGH outputted from the latch and a signal set to HIGH which indicates that the router has no receive data received from a network. The parallel processor system performs AND operation on the outputs of the AND gates of all the processing devices, and detects that a data transmit/receive processing is completed among all the processing devices according to the results of AND operation.

Parallel processor system

A parallel processor system is composed of N processors, N memories and the interconnection where N.times.N data buffers are two-dimensionally placed. Each data buffer provides a data memory with an empty signal and an AND gate. Each memory outputs the transmit completion signal. This signal is input into the corresponding N data buffers and is ANDed with the corresponding empty signal. Each processor inputs the transfer completion signal. This signal is produced by logical-OR among outputs of the AND gates of the corresponding N data buffers. By monitoring the transfer completion signal, each processor recognizes the end of data transfer as data transmission to the corresponding processor ends.

Parallel processor system for quickly detecting the termination of data

A plurality of data latch circuits each used to store row data for one page from a memory cell array are provided, each data latch circuit being allotted to a data processor. An address is given in a multiplexed manner of a row address RA and a column address CA. Data in each data latch circuit is updated when the row address RA is given while the data latch circuit is selected.

Page memory device capable of short cycle access of different pages by a

Parallel processor system for detecting the end of data transmission

In a data transmission device, before the starting of data transmission, a data conduct device detects an external bus, and an address comparator section compares the value of the address signal line with the output values of the parameter memory section. As the result of the comparison, when it is judged that the data to be transmitted is present on the external bus, the address comparator section transmits a write-execution signal to a bus control unit so that the bus control unit writes the data present on the external bus together with the validity bit thereof into the data memory device. In the period of data transmission, when the data assigned to the address produced by an address generator is present in the data memory device, the data is transmitted to the external destination, and on the other hand, when the data assigned to the address is absent in the data memory device, the bus control unit gains access to the external memory for obtaining the data corresponding to the address, so that the data obtained from the external memory is transmitted to the external destination.

Data transmission system which prefetches data to be transferred

A method of data transfer applicable to processing elements which are interconnected by a network to form a multiprocessor system, whereby when a datum is to be transferred from a processing element to the network, the datum is sent to a transfer controller of the processing element at the same time that it is being read out from memory to be used by the processor of the processing element, or as it is being generated from the processor and written into memory. Thus, the system performance can be substantially improved, since the time required to execute each data transfer can be 'hidden' within the processor execution time.

Method and apparatus for data transfer between processor elements

A data transfer apparatus is capable of DMA-transferring the transferable data sequentially generated by a processor. In the data transfer apparatus is provided a counter or an address latch for storing data corresponding to the upper limit (or lower limit) of the address of the transferable data. The content of this counter or latch and the content of the DMA address counter are sequentially compared and transferred, and when these values finally become equal to each other and there is no longer new transferable data, the DMA transfer is stopped and a transfer request is retained. By this constitution, the data transfer between the processor and a device which requires the data generated by the processor may be done instantly and asynchronously.

Data transfer apparatus having a transferable data counter

The buffer device array includes plural buffer devices connected to a bus, wherein the buffer devices hold the respective device addresses and device selection signals in the course of a data transfer operation and subsequently the device addresses and device selection signals held in the devices are used for inspecting devices with respect to whether they can be used for the next data transfer operation, thus enabling the data transfer operation and checking of device status for the next data transfer to be performed in a pipeline fashion and significantly increasing the efficiency of the data transfer operation and of the overall bus utilization.

Data buffer device using first-in first-out memory and data buffer array

A FIFO memory using one of the ports of a RAM having two or more ports for writing and another port for reading is disclosed. Writing into the FIFO memory is done instantly, while reading from the FIFO memory is effected by holding the output of the preliminarily accessed RAM until the end of a reading operation. The output of the RAM is updated by a request from outside and according to the state of the FIFO memory, and this operation is done simultaneously with reading or writing.

First-in-first-out memory capable of simultaneous readings and writing

An integrated circuit having a latch circuit with a selection function includes a selection circuit having a plurality of logic circuits each capable of presenting three output states depending on a selection signal supplied thereto, a latch circuit having a bistable circuit composed of first and second logic inverting circuits, and a connection system for supplying an output of the selection circuit to an input of the latch circuit. An output resistance of the second logic inverting circuit is set to be at least ten times as high as an output resistance of any one of the logic circuits which make up the selection circuit.

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Osaka, Japan

Katsuyuki Kaneko