Hitachi, Ltd.

Other

Hitachi Ulsi Systems Co., Ltd.

Hitachi Tohbu Semiconductor, Ltd.

Katsuyuki Asaka

Makoto Yoshida

Toshihiko Takakura

Tsuyoshi Fujiwara

Yoshinori Hoshino

Kazutoshi Oomori

Yasuhiro Nariyoshi

It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, disclosed is a method in which, e.g., a high density plasma silicon oxide film is deposited on wirings (e.g., a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell) by means of a high density plasma CVD technique, at a first temperature, and the structure is subjected to RTA (heat treatment) at a second temperature higher than the first temperature (e.g., 750&#xb0; C.). Via holes are then formed in the high density plasma silicon oxide film, and first and second conductive films are then formed, the first conductive film being formed in the via holes and at a third temperature lower than the first temperature. The first and second conductive layers are then polished to remain selectively within the via holes. In heat treating the high density plasma silicon oxide film, the temperature is raised from the first temperature to the second temperature at a maximum speed of 60&#xb0; C./second or less.

Method for manufacturing semiconductor integrated circuit device

It is desirable to prevent breakage and separation of wiring of a semiconductor integrated circuit device, such as a bit-line of a DRAM. To accomplish this, an HDP silicone oxide film is deposited on a bit-line that is connected to the source and drain region of a memory cell selection MISFET of a DRAM memory cell by means of a high density plasma CVD technique, and the structure is subjected to RTA (heat treatment) at 750&deg; C. The surface is polished, and then a capacitor to be connected to the other of the source and drain region of the memory cell selection MISFET is formed. As a result, even when a tantalum oxide film, that serves as a capacitance insulating film of the capacitor, is subjected to heat treatment, the film stress exerted on the bit-line is reduced, and breakage and separation of the bit-line are prevented.

A plurality of first contact holes reaching an n -type semiconductor area used as the source of a MISFET employed in a logic-DRAM mixture LSI and a plurality of second contact holes reaching another n -type semiconductor area used as the drain of the MISFET are bored through an insulation layer created over a gate electrode of the MISFET. A conductive film on the same layer as a bit line shunts the n -type semiconductor area used as the source through the first contact holes. Another conductive film shunts the n -type semiconductor area used as the drain through the second contact holes.

Semiconductor integrated circuit device and process for manufacturing the same

Semiconductor integrated circuit device and process for manufacture of the same

A plurality of first contact holes reaching an n,-type semiconductor area used as the source of a MISFET employed in a logic-DRAM mixture LSI and a plurality of second contact holes reaching another n,-type semiconductor area used as the drain of the MISFET are bored through an insulation layer created over a gate electrode of the MISFET. A conductive film on the same layer as a bit line shunts the n,-type semiconductor area used as the source through the first contact holes. Another conductive film shunts the n,-type semiconductor area used as the drain through the second contact holes.

Growing community of inventors

Ome, Japan

Katsuyuki Asaka