Matsushita Electric Industrial Co., Ltd.

Katsuyoshi Tara

Akiyoshi Tamura

Tadayoshi Nakatsuka

Toshiharu Tambo

Takahiro Kitazawa

A semiconductor device whose insertion loss is reduced and isolation characteristics are improved in a high frequency band by reducing the capacitance component when an FET is off is provided. FETs () having a gate electrode with a gate length of not more than 0.8 &#x3bc;m are formed on a semiconductor substrate in which a buffer layer () having an impurity concentration of at least 10cmand at most 10cmis formed on a semi-insulating semiconductor () having at least 10cmand at most 10cmp-type or n-type impurities and an active layer () having a p-type or n-type impurity concentration of at least 10cmand at most 10cmis formed on the buffer layer. N FETs are combined with each other, and when 1&#x2266;m&#x2266;n&#x2212;1 (n and m are integers, n&#x3e;1), a drain terminal of an m-th FET is connected to a source terminal of an (m+1)th FET, resistors () are connected to the gate electrodes of all of the first to n-th FETs, and all of the other ends of the resistors are coupled to the same electric potential.

Growing community of inventors

Kyoto, Japan

Katsuyoshi Tara