Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Katsuyoshi Mitsui

Takashi Kono

Kiyohiro Furutani

Masahide Inuishi

Takeshi Hamamoto

Masahiro Shimizu

Katsuhiro Tsukamoto

Masatoshi Yasunaga

Kiyoto Watabe

Hiromi Itoh

Masanobu Iwasaki

Akira Tokui

Yomiyuki Yama

Shigeki Komori

Takayuki Miyamoto

Ikuo Ogoh

Yuichiro Komiya

Shinichi Jinbo

A semiconductor device includes a voltage control and oscillation circuit oscillating at a frequency according to a first control voltage to output an oscillation signal, a frequency/voltage conversion circuit receiving the oscillation signal from the voltage control and oscillation circuit and converting a frequency of the oscillation signal into a voltage, a control voltage generation circuit generating a new second control voltage having a level between that of the voltage converted by the frequency/voltage conversion circuit and that of a second control voltage generated previously, and an analog integration circuit integrating the second control voltage to generate the first control voltage and outputting the first control voltage to the voltage control and oscillation circuit.

Semiconductor device outputting oscillation signal

An internal power supply potential generating circuit includes: a control potential generating circuit having four MOS transistors connected in series between a node and a ground potential line, and controlling a pull-up transistor and a pull-down transistor in order that a potential at an output node coincides with a control potential; a monitor potential generating circuit having four MOS transistors connected in series between a prescribed node and a ground potential line, and generating a monitor potential; a potential dividing circuit generating a potential &#xbd; times a reference potential; and a VCC1 generating circuit controlling a potential at the prescribed potential in order that the monitor potential becomes the reference potential. Therefore, an output potential can be controlled with correctness.

Potential generating circuit capable of correctly controlling output potential

A VBB control circuit includes an intermediate potential generation circuit receiving a substrate potential VBB which is a negative potential and outputting a divided potential between a power supply potential INTVDD and a ground potential, and an inverter receiving the divided potential and determining whether the substrate potential is higher or lower than a desired value. A logic threshold value of the inverter is (&frac12;)&times;INTVDD. If a relationship of VBB&equals;VREFB&minus;(&frac12;)&times;INTVDD is satisfied, the divided potential accurately becomes (&frac12;)&times;INTVDD. Thereby, it is possible to realize a semiconductor device including a detection circuit which can arbitrarily select a detected potential of the VBB by changing VREFB and which is less influenced by a change in manufacturing conditions.

Semiconductor device having substrate potential detection circuit less influenced by change in manufacturing conditions

An internal power supply potential generating circuit includes: a control potential generating circuit having four MOS transistors connected in series between a node and a ground potential line, and controlling a pull-up transistor and a pull-down transistor in order that a potential at an output node coincides with a control potential; a monitor potential generating circuit having four MOS transistors connected in series between a prescribed node and a ground potential line, and generating a monitor potential; a potential dividing circuit generating a potential 1/2 times a reference potential; and a VCC generating circuit controlling a potential at the prescribed potential in order that the monitor potential becomes the reference potential. Therefore, an output potential can be controlled with correctness.

In a semiconductor device, a time-counting circuit counting a prescribed time in transition to a low-power operation mode includes a CR-type time constant circuit and a complementary NOR gate. The time-counting circuit causes electric charges to be released from a capacitive element through a resistance element when a prescribed signal attains L level. As release of the electric charges continues, the NOR gate operates, a power control signal is output at L level, and the semiconductor device makes a transition to the low-power operation mode. Thus, since the time-counting circuit does not include a multi-stage delay circuit and a latch circuit for time-count, power consumption is low, and circuit area is small. Consequently, the semiconductor device capable of transition to the low-power operation mode can simultaneously implement lower power consumption and smaller circuit area.

Semiconductor device with a low-power operation mode

In order to stably generate a high voltage of a prescribed level, a Vpp detection circuit which is activated in response to an activation signal for comparing the high voltage with a reference voltage is forcibly brought into an active state for a prescribed period under control of an initial control circuit.

Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor

The boosting circuit provided in a semiconductor device includes a ring oscillator generating a pump clock having constant periods, a pump capacitor for performing a boost operation, and a pump capacitor input control unit provided between one electrode of the pump capacitor and the ring oscillator. The pump capacitor input control unit fixes one electrode of the pump capacitor to a prescribed voltage to apply stress of a desired level to the pump capacitor in response to a control signal that is activated at the time of burn-in test.

Semiconductor device including power supply circuit conducting charge pumping operation

An address generating circuit of a DRAM includes five fuses, a trimming switching circuit generating five signals in accordance with whether or not each fuse is blown, a voltage converting circuit generating a control voltage of a level corresponding to the five signals, a voltage control oscillation circuit generating a clock signal of a cycle according to the control voltage, and an address counter generating an address signal in synchronization with the clock signal. Thus, unlike a conventional example, a plurality of counting circuits and a detection circuit are eliminated, resulting in reduction of power consumption and circuit scale.

Semiconductor memory device having self-refresh mode

In the present semiconductor integrated circuit device, a buffer is provided between a constant-current source circuit and an internal circuit that becomes a source of noise. The buffer controls the potential of an output node such that the potential of the output node becomes the bias potential. Even when noise is generated on the bias potential line when the internal circuit is in operation, the buffer dampens the noise. Thus, the noise generated in the internal circuit is prevented from adversely affecting the constant-current source circuit, and a stable operation of the internal circuit itself is achieved.

Semiconductor device having a constant-current source circuit

A semiconductor memory device includes a voltage detection circuit. The voltage detection circuit uses a voltage division circuit to derive from a test command voltage forming a test command signal EXTSH a voltage fraction which is one-third of the original voltage and uses another voltage division circuit to derive from an external supply voltage a voltage fraction which is a half of the original voltage. The two voltage fractions are compared by a comparison circuit of differential amplification type to detect the test command voltage and cause transition of a test target circuit of the semiconductor memory device to a test mode. P channel MOS transistors constituting the voltage division circuits all operate in resistance mode. The test command signal of high-voltage can thus be detected.

Semiconductor memory device capable of detecting high-voltage test command signal

A through-current Ic of a comparator circuit is switched in accordance with a response speed required with respect to a current consumption. Additionally, a through-current Is of a shifter circuit, which sends to the comparator circuit an output signal at an appropriate level transmitting a difference between an internal power supply potential Vdd and a reference potential Vref is switched according to the required response speed. When a device is in a standby state requiring a small current consumption in internal power supply potential Vdd, both through-currents Ic and Is are set small so that the whole current consumption can be further reduced.

Semiconductor memory device allowing reduction in current consumption

An internal power supply circuit produces an internal power supply voltage from an external power supply voltage. A voltage level control circuit controls a voltage level and a temperature characteristic of the internal power supply voltage generated by the internal power supply circuit. The internal power supply circuit produces the internal power supply voltage having a negative or zero temperature characteristic in a low temperature region and a positive temperature characteristic in a high temperature region. The voltage level control circuit includes a structure optimizing a capacitance value of a sense power supply line stabilizing capacitance for driving a sense amplifier circuit, a level converting circuit determining the lowest operable region of the external power supply voltage of the internal power supply circuit, or a structure forcedly operating the internal voltage down converter upon power-on. The internal power supply voltage at a desired level is stably produced with a small occupied area and a low current consumption.

Semiconductor device having an internal voltage generating circuit

A control circuit & mode register outputs a signal responsive to each command to a VDC control circuit. The VDC control circuit outputs a signal PWRUP changing the quantity of a through current Ic of a comparator stored in a VDC in response to the command. The VDC control circuit internally generates a signal of which pulse width corresponds to a prescribed delay time, in response to input of the command. Therefore, activation of each bank may not be monitored but current consumption can be reduced by preferably controlling a power supply current while minimizing the number of delay circuits and wires.

Semiconductor memory device having voltage down convertor reducing current consumption

A Vpp level detecting circuit detects a potential on a Vpp trunk line which is provided commonly to a plurality of memory array banks for supplying a boosted potential thereto, and a boosted potential pump circuit supplies a current to the Vpp trunk line in accordance with a result of the detection. Since the position on the Vpp trunk line where the Vpp level detecting circuit performs the monitoring is substantially equally spaced from the respective memory blocks, an influence caused by an active state of the memory array bank can be suppressed during control of the potential on the Vpp trunk line.

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Hyogo, Japan

Katsuyoshi Mitsui