Texas Instruments Corporation

Katsuyoshi Andoh

Yoichi Miyai

Katsushi Boku

Masayuki Moroi

A method is provided for accurate patterning of photoresist during lithography process. A photoresist layer is deposited on a surface of a semicondictor wafer. The photoresist layer is then illuminated using a lithography apparatus including a mask, a two-thirds annular aperture stop and a quadra pole aperture stop. Portions of the photoresist layer are removed to provide a resulting patterned photoresist layer.

Method for accurate patterning of photoresist during lithography process

A DRAM uses arcuate moats 18 and wavy bit lines 28, 30 for the array of memory cells. A bit line contact 20 occurs at the apex of the moat and storage node contacts 22, 24 occur at the ends of legs 40, 42 extending from the apex. The wavy bit lines have alternating crests 32, 36 and troughs 34, 38. The bit lines are arranged over the moats with the troughs of each bit line overlying and contacting the apexes of each moat and the crests avoiding any moat. The crests and troughs of the bit lines are offset from one another. In a half-pitch pattern, the troughs of one bit line lie adjacent to the crests of the next bit line. The moats are concave between the legs and the angle between the legs is between about 140 and 170 degrees. The angle between the crests and troughs of the bit lines is between about 110 and 160 degrees. In one embodiment, the central portion 70 between the areas surrounding the storage node contacts is about 10% wider than the areas surrounding the storage node contacts.

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Tokyo, Japan

Katsuyoshi Andoh