Mitsubishi Denki Kabushiki Kaisha

Katsuya Shiga

Shigehisa Yamamoto

Naofumi Murata

A test structure for insulation-film evaluation has a CCD structure comprising a semiconductor substrate ( ), a gate insulating film ( ) to be evaluated which is formed across the main surface of the semiconductor substrate ( ), a plurality of gate electrodes ( ) equally spaced in this order on the gate insulating film ( ), a wire ( ) connected to the gate electrodes ( ), a wire ( ) connected to the gate electrodes ( ), and a wire ( ) connected to the gate electrodes ( ). The test structure further comprises a read circuit ( ) including an inverter ( ) and other elements connected to the output stage of the CCD structure. This test structure allows simple failure location.

Test structure for insulation-film evaluation

A semiconductor device testing method using a semiconductor device testing apparatus that can improve the contact characteristic between probe needles and power-supply terminals and signal terminals while ensuring efficiency of product utilization of a tested wafer. Provided on a probe wafer (4) are bumps (5) formed in the same positions in mirror symmetry as the positions of pads (3) formed in individual chips (2) on a tested wafer (1), a common interconnection (6) for interconnecting bumps (5) to be supplied with the same power supplies and signals, and terminals (7) connected to the common interconnection (6) to supply power supplies and signals to the common interconnection (6) from the outside. The bumps (5) come in contact with the pads (3) in the chips (2) when the probe wafer (4) and the tested wafer (1) are put together. The common interconnection (6) supplies the power supplies and signals for a burn-in test to the pads (3) in the chips (2).

Method of testing semiconductor devices

An object is to obtain a semiconductor device testing apparatus that can improve the contact characteristic between probe needles and power-supply terminals and signal terminals while ensuring efficiency of product utilization of a tested wafer. Provided on a probe wafer (4) are bumps (5) formed in the same positions in mirror symmetry as the positions of pads (3) formed in individual chips (2) on a tested wafer (1), a common interconnection (6) for interconnecting bumps (5) to be supplied with the same power supplies and signals, and terminals (7) connected to the common interconnection (6) to supply power supplies and signals to the common interconnection (6) from the outside. The bumps (5) come in contact with the pads (3) in the chips (2) when the probe wafer (4) and the tested wafer (1) are put together. The common interconnection (6) supplies the power supplies and signals for a burn-in test to the pads (3) in the chips (2).

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Tokyo, Japan

Katsuya Shiga