Toshiba Memory Corporation

Kioxia Corporation

Katsuya Ohno

Kenta Yasufuku

Konosuke Watanabe

Satoshi Kaburaki

Yohei Maruyama

Hiroshi Katougi

A memory system includes a nonvolatile semiconductor memory, a controller that controls the nonvolatile semiconductor memory, and a temperature sensor that acquires an operating temperature of at least one of the nonvolatile semiconductor memory and the controller. The controller calculates a temperature parameter based on operating temperatures acquired by the temperature sensor over a period of time, and switches between a plurality of operation settings in which electric power consumptions of the memory system vary, based on the temperature parameter.

Memory system

A memory system includes a first memory chip that includes a first temperature sensor, and a memory controller that includes a second temperature sensor. The memory controller is configured to: perform, at a first timing, a first temperature acquisition process including acquiring a first measured temperature using the first temperature sensor or the second temperature sensor; select one of the first temperature sensor and the second temperature sensor for a second temperature acquisition process based the first measured temperature; and perform, at a second timing later than the first timing, the second temperature acquisition process including acquiring a second measured temperature using the selected one of the first temperature sensor or the second temperature sensor.

A storage device that can be connected to a host device includes a plurality of nonvolatile memories. Each nonvolatile memory includes first memory cells connected to a first word line and second memory cells connected to a second word line. The second word line is adjacent to the first word line. A method of operating the storage device includes maintaining parity data for the data that has been written to the first memory cells, and, upon detecting a failure in the writing of data to the second memory cells, restoring the data written to the first memory cells using the parity data.

Storage device that restores data lost during a subsequent data write

According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to manage a first cache which stores a part of a logical-to-physical address translation table in the nonvolatile memory. The first cache includes cache lines each including sub-lines. Each of entries of a first cache tag includes bitmap flags corresponding to the sub-lines in the corresponding cache line. Each bitmap flag indicates whether data of the logical-to-physical address translation table is already transferred to a corresponding sub-line. The controller determines a cache line including the smallest number of sub-lines to which data of the logical-to-physical address translation table is already transferred, as a cache line to be replaced.

Memory system controlling a cache of a nonvolatile memory

A storage device that can be connected to a host device includes a plurality of nonvolatile memories. Each nonvolatile memory includes first memory cells connected to a first word line and second memory cells connected to a second word line. The second word line is adjacent to the first word line. A controller in the storage device is configured to maintain parity data in a memory area of the host device for the data that has been written to the first memory cells, and, upon detecting a failure in the writing of data to the second memory cells, restore the data written to the first memory cells using the parity data from the memory area of the host device.

A storage device includes a plurality of nonvolatile memories each of which includes first memory cells connected to a first word line and second memory cells connected to a second word line that is adjacent to the first word line, and a controller. The controller is configured to maintain parity data for data written in the first memory cells of the nonvolatile memories, and when carrying out data writing in the second memory cells connected to the second word line in a targeted nonvolatile memory, which is one of the plurality of nonvolatile memories, upon detecting a failure in the data writing therein, carrying out restoration of data that were written in the first memory cells of the targeted nonvolatile memory using the parity data.

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Yokohama Kanagawa, Japan

Katsuya Ohno