Sony Corporation

Sony Electronics Inc

Katsuya Nakashima

Shumpei Kohri

Toshiyuki Nishihara

Yukihisa Tsuneda

Yoshifumi Miyajima

Kazuhiro Suzuki

Kazumi Sato

Satoshi Yamakawa

Mu-Hsiang Huang

Hideki Hara

Akira Nakagawara

Masahiro Ichihashi

Hisanobu Tsukazaki

Takashi Akai

Toshifumi Nomura

A semiconductor laser driving circuit supplies a drive current to a semiconductor laser diode connected to an output terminal based on an input signal inputted thereto through an input terminal, thereby controlling the semiconductor laser diode. The semiconductor laser driving circuit includes a first supply portion supplying a bias current, and a first supply signal having a frequency component whose frequency is equal to or lower than a first frequency of the input signal, and a second supply portion supplying a second supply signal having a frequency component whose frequency is higher than a second frequency of the input signal.

Semiconductor laser driving circuit and semiconductor laser device including the same

A semiconductor laser drive circuit controlling a semiconductor laser diode connected to an output terminal by providing a drive electric current to the semiconductor laser diode includes: a constant electric current source configured to provide an electric current to the output terminal, the constant electric current source being connected to a first electric power terminal and the output terminal; a current sinking circuit connected to the output terminal and a second electric power terminal; a current sourcing circuit configured to provide a predetermined electric current to the output terminal or the current sinking circuit, the current sourcing circuit being connected to the first electric power terminal and the output terminal; and a terminating resistor having a resistance component equal to that of the semiconductor laser diode, the terminating resistor being connected to the circuit sinking circuit and the current sourcing circuit.

Semiconductor laser drive circuit and semiconductor laser apparatus

A file storage apparatus capable of restoring integrity of file management information even when a power supply abnormality occurs without lowering the write speed. When updating meta data stored in an HDD, log data for reconstructing the meta data after update from the meta data before update is written into a non-volatile RAM (NVRAM), then, after this writing is completed, the update is executed. Accordingly, even when the update use meta data temporarily stored in a cache memory is partially lost due to trouble such as a power supply abnormality and when update of the meta data of a hard disk is incomplete, the log data corresponding to the meta data for the update is held in the NVRAM, so it becomes possible to restore the integrity of the meta data on the hard disk by using this log data.

File storage apparatus for storing file data and management information

A semiconductor device and a data storage apparatus are provided. A semiconductor device includes: a cell array configured to have cells for data storage arranged in an array; at least one buffer configured to latch read data of the cell array in units of pages; an output circuit configured to output read data; and a data transfer circuit configured to sequentially transfer read data in units of pages latched in the buffer to the output circuit, wherein the data transfer circuit includes: at least one layer of a scan register train including a plurality of serially connected scan registers having a register and a multiplexer connected to each other to operate for each of clocks, wherein an output of the multiplexer is connected to an input of a register, and an input of a multiplexer is connected to an output of a register in a next previous stage.

Semiconductor device and data storage apparatus

A method and apparatus are provided for a programmable impedance control circuit. In one example of the apparatus, a programmable impedance control circuit of an output driver of an input/output interface is provided. The programmable impedance control circuit includes a pull-up impedance programmed according to a multi-stage emulator and a pull-down impedance programmed according to the multi-stage emulator. The multi-stage emulator includes a first stage for calibrating a pull-up PMOS impedance at a voltage level Voh, a second stage for calibrating a pull-up NMOS impedance at a voltage level Vol, a third stage for calibrating a pull-down NMOS impedance at the voltage level Vol, a fourth stage for re-calibrating the pull-up NMOS impedance at the voltage level Vol, and fifth stage for calibrating a pull-down PMOS impedance at the voltage level Voh.

Programmable impedance control circuit calibrated at Voh, Vol level

A storage device including a ferroelectric memory cell array including a plurality of memory cells; sense amplifiers connected to the bit lines and selected by a column address; an internal counter able to generate the column address; and a control part controlling data access, wherein the control part accesses data by a first processing of reading out a plurality of words of data from memory cells of a word line and a plate line selected according to a row address and storing it in the sense amplifiers, a second processing of selecting sense amplifiers from the column address and inputting/outputting data with the outside, and a third processing of writing back the data of the sense amplifiers into the memory cells, with data being continuously input or output and transferred by repeatedly executing the second processing using the column address generated in the internal counter for a group of words read out to the sense amplifiers at the first processing, and a file storage device and a computer system utilizing such a ferroelectric memory.

Ferroelectric memory capable of continuously fast transferring data words in a pipeline

According to the present invention, an input buffer circuit comprises a first and a second buffer circuits operated at different first and second drive voltages and connected in turn, and an output potential control circuit is provided for carrying out a control so that, in spite of a voltage value of the first drive voltage, a threshold of an output potential of the first buffer circuit becomes a threshold of an input potential of the second buffer circuit. Further, the output potential control circuit is configured such that the first buffer circuit is constituted by a pair of complementary current mirror amplifiers, and comprises feedback control means for carrying out feedback-control to the generation of the output potential for the first buffer circuit on the basis of an output potential on a reference side of this current mirror amplifier.

Input buffer circuit, and semiconductor apparatus having the same

By providing a test circuit including a reference timing generator, a phase error detector, and a comparator, the output signal of the comparator is set in response to the timing of level change of the result of processing of the functional circuit. The phases of the reference pulse generated by the reference timing generator using a control signal as a trigger and the output signal of the comparator by the phase error detector are compared, and the level of a judging signal is set according to the result of the comparison. The judging signal is held temporally by a register, then output to an output pin through a buffer. Using a selector, the held signal of the register is output during the test operation, while the result of processing of the functional circuit is output during normal operation. As a result, it is possible to detect the quality of the chip without using an expensive LSI tester.

Semiconductor device with test circuit for high accuracy chip testing

A sense amplifier is provided with a trimming capability to provide a semiconductor memory device capable of a reading operation at higher speeds than related-art technology. A trimming means (8) is provided for controlling a trimming block (7) in a sense amplifier (5) to perform a trimming operation. A fuse is used for the trimming means (8). The fuse is cut at a necessary position at any given time after fabrication, thereby allowing initialization for reducing the input offset of the sense amplifier (5).

Semiconductor memory device provided with a sense amplifier having a

A memory device comprising memory cells associated with word lines for storing data. A timer is connected to determine the length of time during which a selected word line(s) is activated. The word line activation time length is shorter in a testing mode than in a using mode.

Semiconductor memory testing apparatus

A semiconductor memory device with an address transition detector comprises a flip-flop circuit (FF) having set and reset input terminals and a delay circuit (3). A pulse signal is input to a set input terminal (S) of the flip-flop circuit (FF) and an output signal (P) of the flip-flop circuit (FF) is input through the delay circuit (3) to a reset terminal (R) of the flip-flop circuit (FF), whereby a constant width signal which is independent of a waveform of an address signal and which responds only to the change of address can be obtained as an address transition signal of a SRAM (static random access memory). An internal circuit of the SRAM is initialized by the constant width signal, thereby preventing a malfunction caused by the fact that an initialization time depends on the waveform of the address signal.

Semiconductor memory device with address transition detector

A power-on reset circuit provides the stable generation of a reset signal without being affected by the rising characteristic of a power-supply voltage. A flip-flop having a pair of cross-connected inverters is used, a common connection point between a diode and a capacitor connected to each other in series is connected to a node, which is one output of the flip-flop, an output signal at a node, which is another output of the flip-flip, is supplied to a reset pulse generator via an inverter, so that a reset pulse is generated based on a detected output signal change.

Power-on reset circuit

A memory device comprising a memory cell for storing data, at least one bit line connected to the memory cell, and a switch normally held in a first condition connecting the bit line to a voltage source. The switch is in a second condition disconnecting the bit line from the voltage source in the presence of a control signal. The memory device also includes a program device for producing the control signal to change the switch from the first condition to the second condition when the bit line has a leakage trouble.

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Nagasaki, Japan

Katsuya Nakashima