Fujitsu Corporation

Fujitsu Microelectronics Limited

Kyushu Fumitsu Electronics Limited

Katsuya Ishikawa

Chikara Tsuchiya

Hideki Kato

Kazuo Asakawa

Hideki Yoshizawa

Hiroki Iciki

Takashi Kawasaki

Yoshihide Sugiura

Hiromu Iwamoto

Toshiharu Matsuda

Hiroyuki Tsuzuki

Yasuhiro Hashimoto

Hideichi Endo

Tatsushi Otsuka

Toru Nakamura

Motofumi Tokuriki

Hideichi Endoh

Tomonori Honjou

A semiconductor memory has a memory unit including a regular cell array having a plurality of memory cells and a decoder for decoding an input address and selecting a memory cell corresponding to the input address in the regular cell array, in which an access operation is performed to the selected memory cell; a defective address storage section which stores a defective address corresponding to a defective bit in the regular cell array; and a replacement address storage section which stores a replacement address corresponding to a replacement bit in the regular cell array. When a supply address supplied to the memory unit matches the defective address, the replacement address, in place of the supply address, is supplied to the memory unit as the input address, according to which the access operation is performed.

Semiconductor memory for relieving a defective bit

In order to realize a JTAG test of a printed board including a semiconductor device having JTAG test unsupported input/output terminals inside thereof, one device is logically divided into two devices such as a JTAG test supported device and a JTAG test unsupported device, boundary scan FFs are inserted between the two devices to be combined with another device configured in the same way and the JTAG test unsupported parts of both devices are equivalently combined to be regarded as one JTAG test unsupported device. Then, this device is sandwiched by the JTAG test supported devices and a JTAG test is conducted.

Device and method for JTAG test

An integrated circuit that enables a reduction in chip size and test time. This integrated circuit comprises an internal circuit; an external memory control circuit for inputting read data from an LSI tester by the use of a read command and for outputting write data to the LSI tester by the use of a write command; a test RAM including a read data storage section for storing the read data inputted from the LSI tester at a low speed and a write data storage section for storing the write data outputted from the control circuit; a test circuit for interpreting the read command and the write command issued by the external memory control circuit, for supplying, at the time of determining that the read data must be inputted to the external memory control circuit, the read data from the test RAM to the external memory control circuit at a high speed, and for supplying, at the time of determining that the write data is outputted from the external memory control circuit, the write data outputted from the external memory control circuit to the test RAM at a high speed; and a test circuit for outputting the write data stored in the test RAM to the LSI tester at a low speed.

Integrated circuit

A fixed-logic signal generated inside an integrated circuit is selectively supplied via selectors (Sm+1 to Sn) to input terminals (INm+1 to INn) of a function macro () for receiving signals whose logic levels are fixed to 'H' or 'L' on at least one test pattern. This eliminates any external input terminal for inputting such fixed-logic signal. When the integrated circuit includes function macros, they can be simultaneously tested with this construction.

Integrated circuit test apparatus

A control circuit of a first chip generates control signals for operating a second chip. The first chip and the second chip are manufactured by mutually different processes and packed in a single package. A test control circuit of the first chip inhibits the control signals from being transmitted to the second chip when the first chip is under test. Consequently, the transistors and other components of the second chip are prevented from undergoing stress during a burn-in test on the first chip, for example. As a result, it is possible to conduct a test on the semiconductor device implementing the first chip and second chip whose test conditions are different, with stress applied to the first chip alone.

Semiconductor device and semiconductor integrated circuit

A fixed-logic signal generated inside an integrated circuit is selectively supplied via selectors (Sm&plus;1 to Sn) to input terminals (INm&plus;1 to INn) of a function macro (1) for receiving signals whose logic levels are fixed to &ldquo;H&rdquo; or &ldquo;L&rdquo; on at least one test pattern. This eliminates any external input terminal for inputting such fixed-logic signal. When the integrated circuit includes function macros, they can be simultaneously tested with this construction.

Fixed-logic signal generated in an integrated circuit for testing a function macro integrated in an integrated circuit

A semiconductor device includes a logic chip having a prescribed function and a memory chip for storing data are mounted in a common package. The logic chip and memory chip are connected through memory access terminals, which are a control signal terminal, address terminal, and data terminal. The logic chip has a logic circuit having prescribed functions and a memory chip testing circuit for performing operation tests on the memory chip. The logic chip also has a selector-output circuit for selecting a memory access signal from the logic circuit and a memory testing access signal from the memory chip testing circuit to output the selected signal to the memory access terminal.

Semiconductor device whereon memory chip and logic chip are mounted, making testing of memory chip possible

An object of the present invention is to provide a power line connection circuit which obtains a desired turn-on resistance and a turn-off resistance without using a complex external circuit. The power line connection circuit provides a MOS transistor arranged in a power supply line, whose continuity is changed by applying a control signal from a control unit; a voltage conversion means for converting the voltage of the control signal; and a clamp means for clamping the converted voltage output from the voltage conversion means so as to have a predetermined voltage difference with respect to the voltage of said power supply line.

Power line connection circuit and power line switch IC for the same

A waveform equalizer includes: a data signal input terminal for receiving an input data signal which is the object of waveform equalization; a plurality of S/H circuits each connected to the data signal input terminal; a sampling control circuit for repeatedly bringing the plurality of S/H circuits, one by one, to a sampling operation state; a selection circuit for selecting outputs of a predetermined number of S/H circuits which are in a hold operation state, respectively, from among the plurality of S/H circuits; a weighting circuit for weighting the outputs of the predetermined number of S/H circuits selected by the selection circuit; and an addition circuit for effecting an addition of outputs of the weighting circuit, thereby obtaining a waveform-equalized data signal from an output end of the addition circuit. By the constitution, it is possible to carry out a waveform equalization with high precision, and to realize a high speed of operation and a reduction in the scale of circuit.

Waveform equalizer

A ring oscillator comprises a plurality of amplifiers connected in a multi-stage connection and each including a pair of output terminals from which first output signals are issued respectively; a pair of input terminals to which another pair of output terminals of a last stage amplifier are connected, respectively, and an amplifying circuit arranged between the output terminals and the input terminals. An oscillating signal can be generated by taking out the respectively corresponding second output signals from the amplifiers and combining these second output signals. The ring oscillator is constructed such that the second output signals are taken out from any middle output terminals in the amplifying circuit, other than the output terminals and the input terminals. Preferably, the amplifying circuit includes differential amplifying units each having a pair of differential transistors and a pair of emitter follower units having emitter follower transistors, respectively, and the second output signals are taken out from any portions among the output portions of the emitter follower units and all stage amplifying units other than the final stage differential amplifying unit.

Ring oscillator having outputs that are selectively combined to produce

An input analog data is applied to a plurality of neuron units in a time division manner. The analog input data is multiplied by digital weight data which can be changed in accordance with the data of the interconnection between units. The products of the time division analog input data and the digital weight data are added in an integrator. While the present sum of the products is output, the previous sum of the products is output simultaneously with the present data, thereby providing outputs in a pipe-line manner. When the output of the first neuron is produced, the second neuron in the same layer produces an output such that the output of the first layer is produced on the output analog bus in a time division manner. This analog neuron unit constitutes an intermediate layer and an output layer. One layer of neuron units can be repeatedly used by feeding back the output of one layer to the input of another layer, then the neuron system operates as a layered structure.

Neuron architecture

An error absorbing system for absorbing errors through a weight correction is provided in a neuron computer for receiving an analog input signal through a first analog bus in a time divisional manner, performing a sum-of-the-products operation, and outputting an analog output signal to a second analog bus. The error absorbing system includes a dummy node for producing a fixed voltage to an analog bus in a test mode. The dummy node is connected to the analog bus of the neural network. An error measuring unit compulsorily inputs 0 volts to the first analog bus through the dummy node in a first state of a test mode and detects an offset voltage produced in an analog neuron processor through the second analog bus. A weight correcting unit, in a second state of the test mode, determines a temporary weight between the dummy node and the neuron processor. The temporary weight is multiplied by the fixed voltage produced by the dummy node, based on an offset voltage of respective neuron processors. The weight correcting unit calculates a correct weight using a gain based on the detection output voltage output from the second analog bus. A weight memory stores the weight corrected by the weight correcting unit.

Error absorbing system in a neuron computer

Neurocomputer with analog signal bus

A detection circuit of amplitude modulated signals comprises a first bipolar transistor having a base connected to an input terminal, a collector connected to a first voltage source providing a first power voltage and an emitter; a second bipolar transistor having a base, a collector connected to the first voltage source, and an emitter which is coupled commonly to the emitter of the first bipolar transistor; an output terminal connected commonly to the emitter of the first bipolar transistor and the emitter of the second bipolar transistor for providing an output signal; a biasing circuit connected to the base of the first bipolar transistor and to the base of the second bipolar transistor for biasing the first and second bipolar transistor; a control circuit having an input terminal connected to the base of the first bipolar transistor for producing a control signal in response to an amplitude modulated signal supplied to the input terminal; and a variable current source having a first end connected to the emitters of the first and second bipolar transistors, and a second end connected to a second voltage source providing a second power voltage which is different from the first power voltage, for causing to flow therethrough a drive current to the second voltage source, wherein the control circuit contols the variable current source by the control signal such that the output signal at the output terminal has a voltage level which increases linearly with increasing amplitude of the input amplitude modulated signal in one of positive and negative half cycles of the amplitude modulated signal and such that the output signal has a constant voltage level in the other of the positive and negative half cycles of the amplitude modulated signal.

Growing community of inventors

Kawasaki, Japan

Katsuya Ishikawa