Nec Corporation

Katsuya Furuki

Nobuyuki Sugiyama

Yoshishige Kitamura

A semiconductor integrated circuit comprises a pair of complementary groups of MOS transistors disposed between first and second reference potentials and switched on and off through a pair of complementary groups of input signals inputted to gates thereof, a first switching transistor switched on and off by a clock signal, and a pair of cross-connected second switching transistors disposed between the reference potentials and connected with the pair of groups of MOS transistors. With this construction, unlike prior art techniques, the semiconductor integrated circuit of the present invention operates with greater speed and reduced power consumption, without increasing the channel width of the constituent transistor, and without the need for an inverted clock signal.

Hi-speed and low-power flip-flop

The present semiconductor logic circuit includes a first-stage logic circuit section comprising of a first precharging transistor, a first grounding transistor, and a first logic element and a second-stage logic circuit section comprising of a second precharging transistor, a second grounding transistor, and a second logic element. The first precharging transistor has the common terminal connected to a power terminal and receives a clock signal at the input terminal. The first grounding transistor has the common terminal connected to the ground and receives a clock signal at the input terminal. The first logic element has the grounding end connected to the output terminal of the first grounding transistor and the output end connected to the output terminal of the first precharging transistor. The second precharging transistor has the common terminal connected to a power terminal and the input terminal connected to the output end of the first logic element. The second grounding transistor has the common terminal connected to the ground and the input terminal connected to the output end of the first logic element. The second logic element has the grounding end connected to the output terminal of the second grounding transistor and the output end connected to the output terminal of the second precharging transistor.

CMOS clocked logic decoder

A programmable logic array has a plurality of column units aligned parallel to each other. Each column unit consists of at least one MOSFET column, and at least one load element aligned vertically. Each MOSFET column has a plurality of MOSFETs aligned vertically. The MOSFETs have at least one common gate electrode. The MOSFETs belonging to two parallel MOSFET columns have a common linear source electrode.

Growing community of inventors

Tokyo, Japan

Katsuya Furuki