Renesas Technology Corp.

Other

Katsuya Furue

Kiyohiro Furutani

Takashi Kono

Tetsushi Tanizaki

Shigehiro Kuge

Shigeru Kikuda

Kazushi Sugiura

A plurality of semiconductor integrated circuits and a plurality of TEG circuits are aligned and provided on a substrate. In the TEG circuit, a built-in test circuit is provided in a region which faces a semiconductor integrated circuit across a dicing line region. The built-in test circuit and the semiconductor integrated circuit are connected by an interconnection which is provided on the dicing line region. The interconnection is cut for isolation into chips.

Semiconductor device capable of shortening test time and suppressing increase in chip area, and method of manufacturing semiconductor integrated circuit device

A semiconductor integrated circuit includes a first pad mounted on a main surface of a semiconductor substrate, a second pad mounted on the main surface and positioned adjacent to the first pad, a pad joint mounted between the first pad and the second pad to connect the first pad and the second pad, a first signal input/output circuit including a first output buffer connected to the first pad, a second signal input/output circuit including a second input buffer connected to the second pad, and a second output buffer connected to the second pad and including an output section having a controllable output impedance, an input/output signal control circuit connected to the first signal input/output circuit and the second signal input/output circuit. The input/output signal control circuit includes a first latch circuit connected to an input section of the first output buffer, a second latch circuit connected to an output section of the second input buffer, and a control switch connected to an input section of the first output buffer and an input section of the second output buffer.

Semiconductor integrated circuit

A semiconductor device testing method is disclosed which comprises a first process , a second process and a third process . In the first process , a test function part of a semiconductor device having a built-in self-test function is subjected to a self-diagnostic test, and a main circuit part of the device in question is tested by its test function part. If the result of either of the two tests on the device turns out to be abnormal, the device in question is rejected as defective. The test results are saved. In the second process , the main circuit part of each semiconductor device rejected as defective in the first process is tested by use of an external test signal. If the result of the test on the semiconductor device judged faulty in the first process turns out to be normal in the second process , then the device in question is judged normal in the third process

Method and apparatus for testing semiconductor devices using improved testing sequence

Growing community of inventors

Tokyo, Japan

Katsuya Furue