Winbond Electronics Corporation

Katsutoshi Suito

Makoto Senoo

Oron Michael

Sho Okabe

Kazuki Yamauchi

Takehiro Kaminaga

Tsutomu Taniguchi

Riichiro Shirota

Jongjun Kim

Youn-Cherl Shin

A semiconductor memory device and an operation method capable of suppressing malfunctions and the like and performing safe operations are provided. A flash memory of the disclosure includes a controller which controls an operation based on a code read from a ROM. The operation method of the disclosure includes detecting whether the code read from the ROM has an error by a CRC processing unit; determining whether to transition to a safe mode when the code having the error is detected; and detecting and correcting the error of the code by an ECC processing unit after transitioning to the safe mode.

Memory apparatus and memory testing method thereof for correcting ROM code having error by ECC processing unit after determined to transition to safe mode

In the disclosure, a data processing system includes a microprocessor and a memory. The integrity of data read from a memory by a microprocessor may be checked. When an instruction address is transmitted from the microprocessor to the memory for reading the instruction data corresponding to the instruction address, predetermined dummy data is also read from the memory while the instruction data is read. The integrity of the instruction data may be check by comparing the predetermined dummy data to a hardwire data that is not stored in the memory. If the dummy data matches the hardwire data, the instruction data read from the memory is determined to be correct.

Data processing system and method for reading instruction data of instruction from memory including a comparison stage for preventing execution of wrong instruction data

A continuous readout method of a flash memory is provided. Selected bit lines (BL, BL, BL, and BL) are masked by three non-selected bit lines when data of a cache memory (C) of a selected page of a memory cell array is read. Selected bit lines (BL, BL, BL, and BL) are masked by three non-selected bit lines when data of a cache memory (C) of the same selected page is read. In this way, each of first page data and second page data read from a plurality of selected pages is continuously outputted.

Semiconductor device and continuous reading method

A continuous reading method of a flash memory is provided, including: after outputting data held in a cache memory (C) of a latch (L) of a page buffer/sensing circuit, data of the cache memory (C) of a next page is read from a memory cell array, and the read data of the cache memory (C) is held in the latch (L). After outputting data held in the cache memory (C) of the latch (L), data of the same next page of the cache memory (C) is read from the memory cell array, and the read data of the cache memory (C) is held in the latch (L).

An NAND flash memory and a reading method thereof capable of high-speed reading of SFDP data are provided. The flash memory includes a memory cell array, a page buffer/reading circuitand a controller. The page buffer/reading circuitincludes a first latch circuit Land a second latch circuit L. The first latch circuit Lkeeps data read from the memory cell array. The second latch circuit Lkeeps data transferred from the first latch circuit L. Just after power is turned on or reset, the controllercontrols data of block/pageof the memory cell array to be kept in the second latch circuit Land controls the SFDP data to be kept in the first latch circuit L. The SFDP data or the data of block/pageis serially output according to an input command.

NAND flash memory and reading method thereof

A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array, a page-reading portion which selects a page of the memory cell array, reads data of the selected page, and transmits the read data to a data-holding portion, and a control portion which controls continuous reading of pages. When a command related to termination of the continuous reading is input, the control portion terminates the continuous reading. When the command related to the termination of the continuous reading is not input, the continuous reading terminates. During a period in which the continuous reading is performed continuously, even if a chip selection signal is toggled, the continuous reading can be performed continuously without inputting a page-data read command.

Semiconductor memory device and continuous reading method for the same

A semiconductor storage device, an operating method thereof, and an analysis system capable of analyzing a defect during a specific operation is provided. A semiconductor chip provided by the disclosure determines that whether the semiconductor storage device is in a power-on mode based on a voltage supplied to an external terminal and executes a power-on sequence when the semiconductor storage device is in the power-on mode. The semiconductor chip then determines that whether execution of a break sequence is set, and if the execution is set, the semiconductor chip executes the break sequence. In the break sequence, a selected operation is executed, so that an operation being executed is stopped at a selected timing. A defect of the semiconductor chip is analyzed in a stopped state.

Semiconductor storage device, operating method thereof and analysis system

A semiconductor memory device, a flash memory and a continuous reading method thereof are provided for achieving a continuous reading of pages in high speed. A flash memory of the invention includes a memory cell array; a page reading element, which selects a page of the memory cell array and reads out data of the selected page to a page buffer/sense circuit; a page information storage element, which stores page information related to a range of a continuous reading; and a control element, which controls the continuous reading of the page. The control element determines whether to resume the continuous reading according to the page information. When it is determined to resume the continuous reading, the continuous reading can still be performed without a page data read command and a page address being inputted even if a chip select signal is toggled.

NAND flash memory device performing continuous reading operation using NOR compatible command, address and control scheme

An erasing method of a nonvolatile semiconductor memory device of the disclosure includes erasing data of a selected memory cell (step S); immediately applying a programming voltage lower than a programming voltage in a programming time to all control gates of the selected memory cell after the erasing step, thereby performing a week programming (step S); performing a erasing verification of the selected memory cell (step S).

Non-volatile semiconductor memory and erasing method thereof

The disclosure provides a NAND flash memory and a reading method thereof, which may read a negative threshold value of a memory cell without using a negative-voltage-generating circuit. The disclosed NAND flash memory includes a sense amplifier, a bit line selecting circuit and an array having a plurality of NAND string units. The disclosed NAND flash memory includes a &#x394;V supplying portion element that applies a positive voltage to a source line, a P well formed with a selected memory cell, and a non-selected bit line which is adjacent to a selected bit line, within a predetermined time period, after the selected bit line is pre-charged and during a reading process.

A non-volatile semiconductor memory includes a memory array, a selecting device selecting a page according to addresses, a data storage device, storing page data, and an output device outputting the stored data. The data storage device includes a first data storage device receiving data from a selected page of the memory array, a second data storage device receiving data from the first data storage device, and a data transmission device configured between the first and the second data storage device. The data transmission device transmits data in a second part of the first data storage device to the second data storage device when data in a first part of the second data storage device is output, and transmits data in a first part of the first data storage device to the second data storage device when data in a second part of the second data storage device is output.

Growing community of inventors

Kanagawa, Japan

Katsutoshi Suito