Nec Corporation

Katsutoshi Seki

Tomoyoshi Kobori

Yuzo Senda

Katsunori Tanaka

Yuki Kobayashi

Kosuke Nishihara

Atsushi Hatabu

James Awuor Oduor Okello

Soji Mori

A receiving circuit () includes: a channel estimation unit () configured to estimate a channel response vector based on a reception signal received via a plurality of antennas (); a covariance matrix estimation unit () configured to estimate a covariance matrix based on the reception signal and the channel response vector; a covariance matrix correction unit () configured to correct the covariance matrix by adding, to the covariance matrix, an offset value with a value in components including off-diagonal elements of the matrix; and a weight multiplication unit () configured to estimate a transmission signal by multiplying a weight based on the channel response vector and the corrected covariance matrix by the reception signal.

Wireless receiving apparatus, wireless communication system, and wireless receiving method

In one embodiment, an FFT circuit () includes a pipeline in which L number of butterfly operational elements each having Single-path Delay Feedback, SDF, architecture are connected with each other. Each of LHF number of butterfly PEs (), corresponding to a first stage to an LHFth stage, is configured to rearrange output data order such that, in units of N/(2) pieces of output data starting from head output data whose Data Flow Graph, DFG, index i is '0', intermediate result data G(i) whose b(i) is 1 is output after intermediate result data G(i) whose b(i) is 0 in the N/(2) pieces of the output data, where N represents the number of FFT points, S represents an integer indicating a stage number, and b(i) represents the Sth bit from the least significant bit in binary representation of the DFG index i.

FFT circuit

In an array processing section, using data strings entered from input ports, a plurality of data processor elements execute predetermined operations while transferring data to each other, and output data strings of results of the operations from a plurality of output ports. A first data string converter converts data strings stored in a plurality of data storages of a data storage group into a placement suitable for the operations in the array processing section, and enters the converted data strings into the input ports of the array processing section. A second data string converter converts the data strings output from output ports of the array processing section into a placement to be stored in the plurality of data storages of the data storage group.

Converting a data placement between memory banks and an array processing section

A processor includes a loop counter that is reset to 0 when a loop instruction for executing a process in a loop from a loop start address to a loop end address is issued, a data memory that receives data that is used for executing a process in the loop, in which the data is transferred from outside, a calculator that uses the data transferred to the data memory to execute the process in the loop, a data counter that increments the loop counter by 1 every time a certain amount of data that is used for executing a process in the loop is transferred from outside to a data memory, and a loop controller that decrements the loop counter by 1 and causes the calculator to execute the process in the loop when a loop count value of the loop counter is not 0.

Processor, and method of loop count control by processor

Disclosed is a processor that is able to efficiently execute DFT operations without having part of a basic operational circuit idle even during non-DFT-operation processing. The processor () has an operational means (operation unit) () and a control means (control unit) (). The operation means () has a plurality of shift addition-and-subtraction means connected such that CORDIC (COordinate Rotation DIgital Computer) operations can be executed. The shift adding-and-subtracting means also execute shift addition-and-subtraction processing of butterfly operations that process shift addition-and-subtraction for one stage or more. The control means () instructs the operation means () to execute either CORDIC operations or butterfly operations, based on a plurality of data received from the outside.

Processor and operating method

A data rearranging circuit includes variable delay means and control means. The variable delay means, by imparting a delay of a number of delay cycles that differs for each input cycle and moreover for each port to each unit of data of a data group that is applied as input to a plurality of ports and in a plurality of cycles, switches the order of the data in the same port and supplies the data as the data group at a predetermined delay. The control means supplies control information that includes the number of delay cycles used in the variable delay means.

Data rearranging circuit, variable delay circuit, fast fourier transform circuit, and data rearranging method

A linear systolic array is added to the lower side of a trapezoid systolic array created by combining a triangular systolic array and a square systolic array. In order to make the connection among the cells fixed, the intermediate result output from each row of the trapezoid systolic array to a lower row is shifted in phase with respect to the intermediate result of the complex MFA algorithm, the phase shift is absorbed by the next row, and the phase shift in the intermediate result output from the last row of the trapezoid systolic array is corrected by the linear systolic array. Each cell is implemented by a CORDIC circuit that processes vector angle computation, vector rotation, division, and multiply-and-accumulate with a constant delay.

Systolic array and calculation method

Disclosed is a CORDIC circuit in which scale correction process is divided into two stages: rough correction and fine correction, and a second-process of a pseudo-rotation process is performed in parallel with the fine scale correction. A range of the fine scale correction is set so that it is not necessary to perform a scale correction with regard to a remaining rotation angle of the first half of the pseudo-rotation process.

CORDIC computation circuit and method

To provide a dynamic image receiving apparatus which receives dynamic image streams coded with inter-frame prediction such as MPEG from a plurality of channels, and collects the dynamic image streams containing intra-frame coded pictures from each channel in a short time. The dynamic image receiving apparatus includes: a time information accumulative processing device which accumulates code receiving time of the intra-frame coded picture of the dynamic image stream, and periodicity time information containing one of or both of presentation time information and decoding time information contained in the dynamic image stream for each dynamic image stream of the plurality of channels; code receiving time predicting devices which predict the code receiving time of the intra-frame coded pictures based on the periodicity time information; and a channel selection control device which controls channel selection of the dynamic image stream to be received based on the predicted code receiving time information.

Dynamic image receiving apparatus, dynamic image receiving method and program

Disclosed is a signal processing system in a base station that receives and processes single carrier or multiple carrier signals from transmitting units in a sectored coverage area with at least one transmit antenna and at least one receive antenna, the signal power gain between transmit and receive antennas within each sector being represented as a channel matrix with path gains. The system comprises: a detection unit that determines if signals from a given target transmitting unit is available in the signal received in a sector, and generates a detect signal for a combination unit; a decision unit that selects size of interference cancellation matrix; and an interference cancellation unit. When the signal from detection unit indicates that signal from a target transmitting unit is in the signal associated with at least two sectors, the decision unit joins channel matrices associated with the sectors to generate a large channel matrix, and using the resulting large channel matrix, the interference cancellation unit eliminates interference or generates originally transmitted signal. When the signal from detection unit indicates that signal from a target transmitting unit is in the signal of only one sector, the interference cancellation unit eliminates interference from the received signal, using the channel matrix associated with the one sector.

Signal processing for multi-sectored wireless communications system and method thereof

A self orthogonal decoding circuit and a method thereof, can be realized with simple circuit construction and can significantly improve error correction performance. The self orthogonal decoding circuit performing decoding for self orthogonal code repeats decoding for the self orthogonal code for a plurality of times.

Self orthogonal decoding circuit and self orthogonal decoding method

A first stage inner code decoder performs a first error correction process for a plurality of inner code words. A first stage outer code decoder performs a second error correction process for a plurality of outer code words. A second stage inner code decoder performs a third error correction process for one or more inner code words whose number of errors has been decreased by the second error correction process and skips the third error correction process for one or more inner code words whose number of errors has not been decreased by the second error correcting process.

Iterative decoding method and iterative decoding apparatus

A decoding circuit and a decoding method thereof can significantly reduce circuit scale and power consumption. The decoding circuit, in which a plurality of code words are transmitted in interleaved manner and a plurality of code words are simultaneously decoded on reception side, comprises a decoder which decodes a plurality of said code words simultaneously.

Decoding circuit and decoding method thereof

In a parallel processing Reed-Solomon encoding circuit that allows an arbitrary parallel processing number to be taken and the parallel processing number optimal to the system to be adopted, the multiplier factors corresponding to the first inputs of the first Galois field product sum circuit to the fourth Galois field product sum circuit are the zeroth to third order coefficients of the generator polynomial G(x). The multiplier factors corresponding to the second inputs are the zeroth to third order coefficients of a polynomial of a remainder from xdivided by the generator polynomial G(x). The multiplier factors corresponding to the third inputs are the zeroth to third order coefficients of a polynomial of a remainder from xdivided by the generator polynomial G(x).

Parallel processing Reed-Solomon encoding circuit and method

For training tap coefficients of an adaptive equalizer of L taps to be used for equalizing an impulse response of a transmission channel (,) to be shorter than v taps, stably and speedily, a training circuit comprises: a transmitter (,) for transmitting a transmission signal (x(D)) produced by converting a frequency-domain transmission vector (X) encoded with a PRBS into a time-domain; a target-impulse-response update means (,) for producing an updated target impulse response (B,) making use of frequency-domain division method referring to windowed tap coefficients (w,(D)), a reception signal (y(D)), and a training vector (X) encoded with a replica of the PRBS; a target-impulse-response windowing means (,) for outputting a windowed target impulse response (B,) together wit a normalization coefficient (S) by windowing and normalizing the updated target impulse response (B,) within L taps in a time-domain; a tap-coefficient update means (,) for updating the windowed tap coefficients (w,(D)) making use of a frequency-domain LMS method referring to the normalization coefficient (S), the windowed target impulse response (B,), the training vector (X&prime;) and the reception signal (y(D)); and a tap-coefficient windowing means (,) for windowing the updated tap coefficients into v taps. By updating the windowed tap coefficients (w,(D)) repeatedly until a certain convergence condition is attained, the windowed tap coefficients (w,(D)) are outputted as the tap coefficients of the adaptive equalizer.

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Tokyo, Japan

Katsutoshi Seki