Hitachi, Ltd.

Renesas Technology Corp.

Other

Hitachi Device Engineering Co., Ltd.

Elpida Memory, Inc.

Hitachi Ulsi Engineering Corp.

Solid State Storage Solutions LLC

Hitachi Maxell, Limited

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Systems Co., Ltd.

Katsutaka Kimura

Tomonori Sekiguchi

Hitoshi Kume

Takeshi Sakata

Kiyoo Itoh

Riichiro Takemura

Toshihiro Tanaka

Toshio Sasaki

Masataka Kato

Takayuki Kawahara

Kazuhiko Kajigaya

Tetsuo Adachi

Tsugio Takahashi

Takashi Kobayashi

Hideaki Kurata

Katsuhiro Shimohigashi

Kazuyuki Miyazawa

Yusuke Jyouno

Naoki Kobayashi

Shunichi Saeki

Jun Etoh

Yoshiki Kawajiri

Keiichi Yoshida

Takao Watanabe

Hiroshi Sato

Hiroaki Kotani

Atsushi Nozoe

Shoji Kubono

Satoshi Noda

Hiroki Fujisawa

Ryoichi Hori

Yoshitaka Nakamura

Toshihiko Tanaka

Toshiaki Yamanaka

Tokuo Kure

Masanori Isoda

Syunichi Saeki

Yoshinobu Nakagome

Satoru Hanzawa

Kazuyoshi Oshima

Yasushi Goto

Tetsuya Tsujikawa

Eiji Takeda

Shigeru Sakairi

Mikio Matoba

Ken Sugawara

Digh Hisamoto

Yasushi Takahashi

Shinichiro Kimura

Hitoshi Tanaka

Takesada Akiba

Naoki Miyamoto

Toshiaki Masuhara

Yoshifumi Kawamoto

Hideo Sunami

Toru Kaga

Masamichi Ishihara

Hidetoshi Iwai

Minoru Nagata

Masaya Muranaka

Masatoshi Ohtake

Katsuro Sasaki

Naoki Ozawa

Takashi Nishida

Kazuya Ito

Hidehito Obayashi

Kiyoshi Aiki

Hiromi Matsuura

Kazuhiro Kondo

Yoshihisa Koyama

Nobuo Hamamoto

Shimpei Iijima

Isamu Orita

Kiyoo Ito

Tadashi Onishi

Hiroshi Kishida

Hisashi Horikoshi

Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Nonvolatile semiconductor memory

In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few each of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.

Semiconductor integrated circuit

In a masking pattern (a) for patterning word and data lines, length is changed between adjacent word lines so as to be shifted from each other at their tips, and furthermore, the tip of each word line is cut obliquely. It is thus possible to prevent the resist pattern from separation and contact of adjacent patterns. Consequently, it is also possible to prevent break failures of patterned lines and short failures between those patterned lines.

Semiconductor device and method for patterning

To enable one non-volatile memory cell to store four-value information, three different kinds of threshold voltages are serially applied to a word line in a verify operation to execute a write operation, the threshold voltages of the memory cell are controlled, and two-value (one-bit) information corresponding to the four-value (two-bit) information to be written are synthesized by a write data conversion circuit for each of the write operations carried out three times. In this way, the four-value (two-bit) information are written into one memory cell, and the memory capacity of the memory cell can be increased. In the information read operation, three different kinds of voltages are applied to a word line, three kinds of two-value (one-bit) information so read out are synthesized by a read conversion circuit and the memory information of the memory cell are converted to the two-bit information.

Nonvolatile semiconductor memory device which stores multi-value information

A semiconductor integrated device having a plurality of memory cells, each including a floating gate, a control gate and an auxiliary gate formed over a side surface of the floating gate through an insulator film. Auxiliary gates coupled to selected memory cells function to generate hot electrons and are alternately arranged with other auxiliary gates functioning to prevent write errors in the non-selected memory cells.

Semiconductor integrated circuit device, production and operation method thereof

A sense amplifier capable of performing high-speed data sense operation with lower power consumption using a minuscule signal from a memory cell even in a case where a memory array voltage is reduced. A plurality of drive switches for over-driving are distributively arranged in a sense amplifier area, and a plurality of drive switches for restore operation are concentratively disposed at one end of a row of the sense amplifiers. A potential for over-driving is supplied using a meshed power line circuit. Through the use of the drive switches for over-driving, initial sense operation can be performed on data line pairs with a voltage having an amplitude larger than a data-line amplitude, allowing implementation of high-speed sense operation. The distributed arrangement of the drive switched for over-driving makes it possible to dispersively supply current in sense operation, thereby reducing a difference in sense voltage with respect to far and near positions of the sense amplifiers.

Semiconductor device

A dynamic RAM incorporates a plurality of dynamic memory cells, each of which comprises a MOSFET having a gate set as a select terminal, one source and drain set as input/output terminals, and the other source and drain connected to storage nodes of a capacitor, a plurality of word lines respectively connected to the select terminals of the plurality of dynamic memory cells, a plurality of complementary bit line pairs respectively connected to the input/output terminals of the plurality of dynamic memory cells, and a sense amplifier array comprising a plurality of latch circuits which respectively amplify differences in voltage between the complementary bit line pairs placed so as to extend in directions opposite to each other from each pair of input/output terminals. Power supply lines are provided in mesh form inclusive of a portion above word drivers.

Dynamic random access memory (DRAM) capable of canceling out complementary noise development in plate electrodes of memory cell capacitors

Semiconductor integrated circuit device including first, second and third gates

Growing community of inventors

Akishima, Japan

Katsutaka Kimura