Fujitsu Corporation

Katsusige Asada

Tsuyoshi Kamada

Yoji Nagase

A plurality of parallel gate bus lines 16n, 16n+1, 16n+2, . . . and a plurality of parallel drain bus lines 18m, 18m+1, . . . are provided. Thin film transistors 14 are disposed near the lower end of sub-patterns 30n, 30n+1, 30n+2, . . . The source electrodes 36 of the thin film transistors 14 are picture element electrodes 12 through contact holes 38. The picture element electrodes 12 are formed at positions which are beyond a next gate bus line 16n, 16n+1, 16n+2, . . . Intermediate electrodes 40 for forming sub-capacitances Cs are formed on the lower ends of the picture element electrodes 12. The thin film transistor matrix device can form sub-capacitances of a large capacitance value and does not reduce fabrication yields.

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Kawasaki, Japan

Katsusige Asada