Texas Instruments Corporation

Katsushi Boku

Yoichi Miyai

Toshiyuki Nagata

Masayuki Moroi

Hiroyuki Yoshida

Yoshihiro Ogata

Takayuki Niuya

Scott Robert Summerfelt

Katsuyoshi Andoh

Ferroelectric memory cells and fabrication methods are provided in which the memory cell comprises a ferroelectric capacitor in a capacitor layer above a semiconductor body, and a cell transistor with first and second source/drains formed in an active region of the semiconductor body. The active region extends along a first axis in the semiconductor body, and the cell includes a gate electrically coupled with a wordline structure that extends along a second axis, wherein the first axis and the second axis are oblique.

Ferroelectric memory cell with angled cell transistor active region and methods for fabricating the same

An open can-type stacked capacitor is fabricated by forming a conductive layer ( ) outwardly of a substantially uneven surface ( ). A step ( ) is formed in an outer surface ( ) of the conductive layer ( ). A base ( ) of a first electrode ( ) is formed by removing a predetermined thickness ( ) of at least part of the conductive layer ( ). The base ( ) is made of a portion of the conductive layer ( ) underlying the step ( ) by the predetermined thickness ( ). A sidewall ( ) of the first electrode ( ) is formed. A dielectric layer ( ) is formed outwardly of the first electrode ( ). A second electrode ( ) of the capacitor is formed outwardly of the dielectric layer ( ).

Method for fabricating an open can-type stacked capacitor on an uneven surface

An open can-type stacked capacitor is fabricated by forming a conductive layer (,) outwardly of a substantially uneven surface (,). A step (,) is formed in an outer surface (,) of the conductive layer (,). A base (,) of a first electrode (,) is formed by removing a predetermined thickness (,) of at least part of the conductive layer (,). The base (,) is made of a portion of the conductive layer (,) underlying the step (,) by the predetermined thickness (,). A sidewall (,) of the first electrode (,) is formed. A dielectric layer (,) is formed outwardly of the first electrode (,). A second electrode (,) of the capacitor is formed outwardly of the dielectric layer (,).

An open can-type stacked capacitor is fabricated on local topology by forming a conductive layer (,) outwardly of an insulator (,) and an access line (,) extending from the insulator (,). A mask (,) is formed outwardly of the conductive layer (,). A first electrode (,) is formed by removing at least part of the conductive layer (,) exposed by the mask (,). The first electrode (,) includes an annular sidewall (,) having a first segment (,) disposed on the insulator (,) and a second, opposite segment (,) disposed on the access line (,). A dielectric layer (,) is formed outwardly of the first electrode (,). A second electrode (,) is formed outwardly of the dielectric layer (,).

Method for fabrication an open can-type stacked capacitor on local topology

A DRAM uses arcuate moats 18 and wavy bit lines 28, 30 for the array of memory cells. A bit line contact 20 occurs at the apex of the moat and storage node contacts 22, 24 occur at the ends of legs 40, 42 extending from the apex. The wavy bit lines have alternating crests 32, 36 and troughs 34, 38. The bit lines are arranged over the moats with the troughs of each bit line overlying and contacting the apexes of each moat and the crests avoiding any moat. The crests and troughs of the bit lines are offset from one another. In a half-pitch pattern, the troughs of one bit line lie adjacent to the crests of the next bit line. The moats are concave between the legs and the angle between the legs is between about 140 and 170 degrees. The angle between the crests and troughs of the bit lines is between about 110 and 160 degrees. In one embodiment, the central portion 70 between the areas surrounding the storage node contacts is about 10% wider than the areas surrounding the storage node contacts.

DRAM COB bit line and moat arrangement

A method for fabricating and for blowing top lead fuses (41 and 42) includes the steps of: (a) forming a conductive top lead fuse (41) on a layer of insulator (45); (b) depositing a layer of top insulator (47) over the top lead fuse at a top to sidewall thickness ratio of approximately 2:1; (c) anisotropically etching the top insulator back universally to a top to sidewall thickness ratio of approximately 1:2. The resulting top lead fuses (30 and 31) are selectively blown explosively out (24) of the top surface of the top insulator.

Sidewall formation process for a top lead fuse

A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100).

Method of manufacturing a semiconductor device

A semiconductor device in which a trench-shaped groove (20) and a depression (100), which is formed by removing at least part of the area above and adjacent to the groove, are formed to be continuous on one side of the semiconductor substrate, in which aforementioned groove and aforementioned depression is buried a polysilicon conductive layer (103), the top of which conductive layer is converted into an insulator (102), the bottom of which insulating film (102) is contained in the depression (100). It is possible to form the element areas according to designs, and it is also possible to flatten the surface without wire cutting in the conductive layer.

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Dallas, TX, United States of America

Katsushi Boku