Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Katsushi Asahina

Masahiro Ueda

Hideki Taniguchi

Shigeki Ohbayashi

Harufusa Kondoh

Toshiaki Hanibuchi

Masashi Ishii

Ryoichi Takagi

Yasushi Hayakawa

Masahiko Hyozo

Takeshi Ooshita

Takuji Komeda

Mitsuo Magane

A terminating resistance element of an LSI chip has an Ntype impurity diffusion region formed at the surface of a P type well at the surface of a semiconductor substrate, an Ntype impurity diffusion layer formed at the surface of the Ntype impurity diffusion region, and a pair of electrodes formed at respective ends at the surface of the Ntype impurity diffusion layer. The Ntype impurity diffusion region has an impurity concentration lower than the impurity concentration of the Ntype impurity diffusion layer. Therefore, the capacitance of the PN junction becomes smaller as compared to the conventional case where the N type impurity diffusion layer is provided directly at the surface of a P type semiconductor substrate. Therefore, reflection and attenuation of an input signal are suppressed.

Semiconductor device

In a transmission signal correction circuit, a first output circuit outputs a data string to outside. A second output circuit for correction is connected in parallel with the first output circuit. The second output circuit receives the data string to add the data string to an output signal of the first output circuit during a period when a control signal is kept generated. A data string detection circuit generates the control signal when detecting a signal sequence, in the data string, that affects a transmission waveform.

Transmission signal correction circuit

Provided is a semiconductor device having an I/O buffer cell capable of performing a timing verification test of high accuracy. A phase comparator (,) compares the phase of data (DATA) and that of a clock (CLK) and outputs a phase comparison result to a first input of an MUX (,). A test mode signal (STM,) inputted from a test mode terminal (,) is provided to the control input of the MUX (,) through a test mode input section (,). The MUX (,) receives at its second input the output signal of an internal logic (,) through a signal input section (,) and, based on the test mode signal (STM,), outputs either the phase comparison result or the output signal of the internal logic (,), to the input section of a driver (,).

A semiconductor integrated circuit, in which an input buffer, an output buffer, and an input/output buffer connected to signal pins respectively each as an object for a DC test are connected to a single DC test pin through discretely provided switches, all the switches are OFF in an ordinary state, and when the DC test is to be performed, the switches are successively turned ON one by one in a state where the DC test pin is connected to an LSI tester. With the operation, various types of DC test such as a pin contest, an input leak test and an output voltage test can be performed by using a LSI tester having a smaller number of pins than a number of pins in an LSI without requiring a connection such that the signal pins as objects for the test are in one-to-one correspondence with the pin electronics in the LSI tester.

Semiconductor integrated circuit

An object is to provide a semiconductor integrated circuit capable of controlling the output resistance value of an output buffer circuit always at a given value without deteriorating the data transmission quality. D latches (60-63, 65-68) in latch circuit portions (16, 17) in an output resistance control output buffer circuit (2) receive an output resistance control trigger signal (STRB) in common at their respective T inputs. The D latches (60-63) also receive pull-up bit control signals (U0-U3) at their respective D inputs, and the D latches (65-68) also receive pull-down bit control signals (D0-D3) at their respective D inputs. The output resistance value of transistors (QU0-QU3) and transistors (QD0-QD3) is controlled with the data latched in the latch circuit portions (16, 17), respectively. The output resistance control trigger signal (STRB) rises to 'H' after a sufficient time has passed after an output resistance control signal determining period in which the pull-down bit control signals (D0-D3) and the pull-up bit control signals (U0-U3) are determined.

Semiconductor integrated circuit having controlled output resistance of

An output buffer circuit for controlling operation of an input and output terminal utilizing a pair of MOS Transistors respectively formed in first and second wells in a substrate. The input and output terminal is connected commonly to the source of the first MOS transistor, to the drain of the second MOS transistor and to the well of the first MOS transistor in order to hold the well at the same potential as the input and output terminal. Also included is a first potential point applying a first potential to the drain of the first MOS transistor and a second potential apply commonly to the source and the well electrode of the second MOS transistor. The resulting structure controls the operating state of the input and output terminal in a manner which allows for an enhanced output potential.

Output buffer circuit

A detecting penetration current causing logic part (12a) gives, when the logic is H level at both nodes (N15, N24), the logical product thereof H to a condition adding part (12b) as an activated detection signal. In the condition adding part (12b), it is confirmed that the activation of the detection signal is longer than a specified time, by a delay circuit (G21) and NAND gate (G22). Consequently, logic H is given to a forced logic presenting part (12c). In the forced logic presenting part (12c), NMOS transistors (Q13, Q14) are turned on, and logic L is given by force to both nodes (N15, N24) to get out of a state where a current would flow.

There is disclosed an input circuit for a semiconductor integrated circuit device wherein a level shift circuit (LS1) adds a constant voltage to an input signal from an input signal terminal (3) and a reference voltage from a reference voltage terminal (4) to output signals, which are in turn amplified by means of a plurality of cascaded, first and second differential amplifier circuits (Dif1, Dif2), and then a difference between the amplified input signal and the amplified reference voltage is applied to a CMOS inverter circuit (In1), which in turn outputs a power supply potential (V.sub.DD) or a ground potential (V.sub.SS) in accordance with the difference, thereby achieving a high-speed operation in response to the binary input signal slightly varying in signal voltage and a normal operation independent of variation of the reference voltage. (FIG. 1 )

Input circuit for processing small amplitude input signals

An input signal is inverted by an inverter in the first stage and an n-channel MOS transistor on the pull up side in a driver is driven, while an output signal of the inverter in the first stage is inverted by an inverter in the next stage and an n-channel MOS transistor on the pull down side is driven. A driving signal is output from a connection point between the n-channel MOS transistor on the pull up side and the n-channel MOS transistor on the pull down side, and an output transistor is driven by the driving signal. Since a gate voltage of the output transistor increases only by a value of a power supply voltage Vdd minus threshold voltage V.sub.T, a rise time and a fall time of a gate potential can be reduced, resulting in improvement in the duty cycle.

Open-drain fet output circuit

An output circuit of a semiconductor integrated circuit device is obtained which can externally produce a signal lager in amplitude than an internal signal amplitude without degrading reliability of miniaturized transistors. A PMOS transistor (23) and an NMOS transistor (24) connected to an output terminal (5) cooperatively output a potential (V.sub.DD2) at a power source or a potential (V.sub.SS) at a ground as output voltage. A potential of an input signal, a potential (V.sub.DD1) at a power source or the potential V.sub.SS at the ground, are converted by a first converting unit (K2) and a second converting unit (K3) to apply to a gate of the PMOS transistor (23). The first converting unit (k2) and the second converting unit (K3) utilize potential developed by an intermediate potential generating circuit and the potential (V.sub.DD1) at the power source to convert the potential of the input signal. Thus, an output signal having a larger amplitude than the input signal amplitude can be produced without applying the potential difference of the potential (V.sub.DD2) from the ground potential (V.sub.SS) to insulated gate transistors (12 to 23) constituting the output circuit between their respective gates and substrate.

Output circuit of semiconductor integrated circuit device

Reliability related problems such as destruction of the insulation film and shortened operating life of the MOSFET are prevented in a case where the voltage of an input signal is larger than a power source voltage for a semiconductor integrated circuit device. Where the voltage of an input signal which is received at an input signal terminal (3) is larger than a power source voltage V.sub.DD1, by causing a voltage drop between source-drain of an N channel MOS transistor (Tr4) which has a gate electrode fixed at the power source voltage V.sub.DD1, the voltage of the input signal is shifted. The shifted voltage is then applied to a gate electrode of an N channel MOS transistor (Tr2). That is, the voltage of the input signal is not directly applied to the gate electrode of the N channel MOS transistor (Tr2). Thus, when the voltage of the input signal is larger than the power source voltage for the semiconductor integrated circuit device, by shifting the voltage of the input signal and thereby preventing application of an excessively large voltage to a gate insulation film, enhanced operation reliability is attained.

Input circuit of semiconductor integrated circuit device

An open drain output circuit includes a package having a reference potential section on at least a portion thereof. An output terminal of the circuit disposed on the package is connected through a load resistor to an external power supply. A common terminal also disposed on the package is connected to an external point of reference potential. A parasitic load capacitance is formed between the common terminal and the load resistor. A field effect transistor having drain, source and gate regions is disposed within the package. The drain and source regions are connected to the output and common terminals, respectively. The conductivity of the drain-source conduction path is variable in accordance with the value of a control voltage applied between the gate and source regions. Connections of the drain and source regions to the output and common terminals, respectively, provide parasitic inductances. Parasitic capacitance is formed between the drain region and the reference potential section and between the source region and the reference potential section. Control voltage generating means generates the control voltage in such a manner that the rate of change of the control voltage decreases as it changes from a high level to a low level and overshoot in the output signal is thereby reduced.

Open drain driver circuit which eliminates overshoot caused by parasitic

Disclosed is an improved Bi-CMOS gate array for increasing integration density. The gate array includes a predetermined region for forming PMOS transistors, a predetermined region for forming bipolar transistors, a predetermined region for forming resistance elements, and a predetermined region for forming NMOS transistors. The resistance element region is formed adjacent to the bipolar transistor region, and, therefore, it is not necessary to provide any interconnection for forming a logic circuit including the resistance element connected to the bipolar transistor. An area occupied by interconnections on the semiconductor substrate is thus reduced, and, therefore the integration density is increased.

Semiconductor integrated circuit device for forming logic circuit

A level conversion apparatus for converting a signal of an ECL level into a signal of a TTL level is disclosed which has source voltages set to a potential corresponding to a lower limit logic swing of the ECL level and a potential corresponding to an upper limit logic swing of the TTL level. This level conversion apparatus includes a reference voltage generating circuit for generating an upper limit reference voltage and a lower limit reference voltage divided from a voltage applied between a source terminal Vcc and a ground terminal, a control signal generating circuit for generating a control signal in response to the ECL level signal, determined by a difference between the upper limit reference voltage and the lower limit reference voltage, and an output switching circuit for carrying out a switching operation in response to the controlled signal. The output switching circuit outputs a signal determined by the potential corresponding to the upper limit logic swing of the TTL level and a ground source.

Method and apparatus for conversion of signal level from ECL to TTL

A Bi-CMOS logic circuit structured by bipolar transistors and insulated gate type transistors includes a first NPN bipolar transistor for charging an output node and a second NPN bipolar transistor for discharging the output node. The first bipolar transistor has a collector coupled to a first power supply and an emitter connected to the output node. The second bipolar transistor has a collector connected to the output node and an emitter coupled to a second power supply. The Bi-CMOS logic circuit also includes at least one P channel insulated gate type transistor provided between the first power supply and a base of the first bipolar transistor for receiving an input signal at its gate, and at least one N channel insulated gate type transistor provided between the output node and a base of the second bipolar transistor for receiving the input signal at its gate. The Bi-CMOS logic circuit further includes a third NPN bipolar transistor for drawing charges out of the base of the first bipolar transistor, and an impedance element for biasing the base of the second bipolar transistor relative to the second power supply. The third bipolar transistor has a collector connected to the base of the first bipolar transistor, a base connected to the base of the second bipolar transistor and an emitter connected to the second power supply. The impedance element includes a fourth N channel insulated gate type transistor having a gate connected to the output node, one conduction terminal connected to the respective bases of the second and third bipolar transistors, and other conduction terminal coupled to the second power supply.

Growing community of inventors

Hyogo, Japan

Katsushi Asahina