Matsushita Electric Industrial Co., Ltd.

The University of Manchester

Matsushita Electrical Industrial Co., Ltd.

Katsura Kawakami

Shigeo Shimazaki

John R Gurd

Etsuko Hirokami

Satoshi Takayama

Hiroaki Kotera

Yuetsu Ochiai

Kazufumi Suzuki

Chika Onodera

A parallel storage allocation method and device in which each space in a memory section that is available for use is associated with a respective allocator and stores an identifier for the respective allocator, data identifying allocators not in use is stored, and a list of allocators associated with spaces which are available for use is maintained. Each time a memory space is no longer in use a check is made to determine the allocator identifier of any already free space which can be combined with the memory space that is no longer in use. A liberate space token is generated which includes a first identifier corresponding to an allocator which is not in use and a second identifier which corresponds to any already free space to be combined. If the list of allocators relative to available space does not contain the allocator having the second identifier, the allocator having the first identifier is entered in the list with details of the no longer in use space. If the list does not contain the allocator having the second identifier, the space that is no longer in use is combined with the space to which the second identifier relates and then the allocator having the first identifier is entered in the list with details of the combined space.

Storage allocation and garbage collection using liberate space tokens

A delay management method and device in which, when a data read request is made relating to data which has not yet reached a memory section, that read request is delayed and sent to a delay management section. The read request data is sent to a free address in the delay management section selected from a store of free addresses in the memory section. The delay management section stores the read request data at the free address. The delay management section communicates free addresses to the memory section.

Delay management method and device

An image processing apparatus includes a memory having a first region and a second region. The first memory region holds original image data. A first calculation device calculates addresses of segments of the first memory region. A second calculation device calculates addresses of segments of the second memory region. The original image data are transferred from the first memory region to the second memory region in accordance with the calculated addresses of the segments of the first and second memory regions. The first calculation device and the second calculation device are mutually independent. The calculation of the addresses of the segments of the first memory region is performed simultaneously with the calculation of the addresses of the segments of the second memory region.

Image processing apparatus

An apparatus for expanding or contracting image data includes an input for storing the image data to be processed, a first barrel shifter for shifting the output data of the input register, a control register for storing a mapping pattern which indicates a position of the image data bits to be extracted in the expansion mode or which indicates the number of times when the image data are to be copied, an expansion and contraction circuit for expanding or contracting the image data by referring to the mapping pattern, and a second barrel register for shifting the output image data of the expansion and contraction circuit before the data are loaded in an output data register.

Image data expanding and/or contracting method and apparatus

Image data is transposed between successively arranged first data points in a first image field and successively arranged second data points in a second image field by a method comprising: (1) successively specifying a first data point (i); (2) summing first control data indicative of a residue with second control data indicative of a constant value; (3.sub.1) if the result of the summation does not exceed a predetermined value, updating the first control data with the summation result and specifying a second data point (j) corresponding to the specified first data point, or (3.sub.2) if the result exceeds the predetermined value, subtracting it from the summation result to update the first control data with the residue, and specifying a second data point (j) which is shifted by one data point with respect to the specified first data point; (4) transferring the image data from the specified first data point to the specified second data point or from the specified second data point to the specified first data point depending on the relative size of the first and second image fields. The steps (1) to (4) are repeated until all the second data points are filled with the image data.

Method and apparatus for processing image data using sum and subtract

A plurality of registers included in a central processing unit are electrically divided into a plurality of register-sets which are arranged in a given order to be used as a stack where one of the register-sets at the top of stack is normally used for executing the program of a main routine. In one embodiment, the data of the register-sets are pushed down for executing interrupt service routines and then popped up for resuming the suspended program. When all of the register-sets are loaded, the data may be saved in a saving region of a main memory, and the saved data may be directly transferred to the top register-set when needed. In another embodiment, actual push down and popping up of data are not performed but one of the register-sets is selectively enabled so that the register-sets function as a stack.

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Yokohama, Japan

Katsura Kawakami