Kabushiki Kaisha Toshiba

Sony Corporation

Toshiba Memory Corporation

Katsunori Yahashi

Atsushi Murakoshi

Tokuhisa Ohiwa

Nobuyasu Nishiyama

Tomoya Satonaka

Noriko Sakurai

Nikka Ko

Masaru Kidoh

Satoshi Nagashima

Tadashi Iguchi

Kouji Matsuo

Toshiyuki Sasaki

Mitsuhiro Omura

Makoto Hasegawa

Keisuke Kikutani

Daigo Ichinose

Junichi Hashimoto

Takuji Kuniya

Masao Ishikawa

Shuichi Taniguchi

Daina Inoue

Jungo Inaba

Takashi Shinyama

Keiichi Takenaka

According to one embodiment, a method is disclosed for manufacturing an integrated circuit device, the method can include forming a mask member on a first film, the mask member having a pattern, performing a first etching on the first film using the mask member as a mask to form a recessed section in the first film, forming a second film covering an inner side surface of the recessed section. The second film has a film thickness of preventing blockage of the recessed section, and performing a second etching on the second film and the first film via the recessed section. The performing of the second etching includes performing a third etching in a condition of an etching rate at a place smaller in curvature radius in the recessed section being lower than an etching rate at a place larger in curvature radius in the recessed section.

Method for manufacturing integrated circuit device

According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body including a plurality of first layers and a plurality of second layers on a substrate. The method includes forming a first slit and a second slit simultaneously by dry-etching the stacked body. The first slit causes a part of the stacked body to have a comb-shaped pattern including a plurality of line parts isolated in a first direction and extending in a second direction. The second slit surrounds the comb-shaped pattern with a closed pattern. The method includes forming a hole in the line parts of the stacked body. The method includes forming a charge storage film and a semiconductor body in the hole.

Method for manufacturing semiconductor memory device

According to one embodiment, a memory cell section includes a memory layer in which a non-volatile memory cell is arranged at an intersecting position of a first wiring and a second wiring to be sandwiched by the first wiring and the second wiring. A first drawing section connects the memory cell section and a first contact section with the first wiring, and a second drawing section connects the memory cell section and a second contact section with the second wiring. A dummy pattern is provided in a layer corresponding to the memory layer immediately below the first and second wirings configuring the first and second drawing sections.

Non-volatile memory device and manufacturing method of the same

A three-dimensional semiconductor device includes a semiconductor substrate, a plurality of conductive layers and insulating layers, and a plurality of contacts. The plurality of conductive layers and insulating layers are stacked alternately above the semiconductor substrate. The plurality of contacts extend in a stacking direction of the plurality of conductive layers and insulating layers. The plurality of conductive layers form a stepped portion having positions of ends of the plurality of conductive layers gradually shifted from an upper layer to a lower layer. The plurality of contacts are connected respectively to each of steps of the stepped portion. The stepped portion is formed such that, at least from an uppermost conductive layer to a certain conductive layer, the more upwardly the conductive layer is located, the broader a width of the step is.

Nonvolatile semiconductor memory device, three-dimensional semiconductor device, and method of manufacturing the same

According to one embodiment, a method for manufacturing a semiconductor memory device includes: forming a stacked body including insulating films stacked alternately with electrode films, a memory hole is made in one portion of the stacked body to extend in a stacking direction, a charge storage layer is provided on an inner surface of the memory hole, a semiconductor member is provided in the memory hole; forming a hard mask on the stacked body, the hard mask has a plurality of holes of mutually different sizes; plugging the smallest of the holes while shrinking the other holes by depositing a mask material; making contact holes by removing a prescribed number of the insulating films and a prescribed number of the electrode films in regions directly under the other holes by performing etching using the mask material and the hard mask as a mask; and filling conductive material into the contact holes.

Semiconductor memory device and method for manufacturing same

According to one embodiment, a semiconductor device includes a substrate, a lower gate layer, a stacked body, a dummy electrode layer, an insulating film, and a channel body. The lower gate layer is provided above the substrate. The stacked body includes a plurality of insulating layers and a plurality of electrode layers alternately stacked above the lower gate layer. The dummy electrode layer is provided between the lower gate layer and the stacked body, made of the same material as the electrode layer, and thicker than each of the electrode layers. The insulating film includes a charge storage film provided on a side wall of a hole formed to penetrate through the stacked body and the dummy electrode layer. The channel body is provided on an inside of the insulating film in the hole.

Semiconductor device and method for manufacturing same

A semiconductor memory device comprises a plurality of transistors having a stacked-gate structure. Each transistor includes a semiconductor substrate, a gate insulator formed on the semiconductor substrate, a lower gate formed on the semiconductor substrate with the gate insulator interposed, an intergate insulator formed on the lower gate, and an upper gate formed and silicided on the lower gate with the intergate insulator interposed. A portion of the transistors has an aperture formed through the intergate insulator to connect the lower gate with the upper gate and further includes a block film composed of an insulator and formed smaller than the upper gate and larger than the aperture above the upper gate to cover the aperture.

Semiconductor memory device and method of manufacturing the same

According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include forming a stacked body by alternately stacking a plurality of insulating layers and a plurality of conductive layers above a substrate and forming a resist film above the stacked body. The method can include plasma-etching the insulating layers and the conductive layers by using the resist film as a mask. The method can include forming a hardened layer in an upper surface of the resist film by plasma treatment using a gas containing at least one selected from a group consisting of boron, phosphorus, arsenic, antimony, silicon, germanium, aluminum, gallium, and indium. The method can include slimming a plane size of the resist film by plasma treatment using an oxygen-containing gas in a state where the hardened layer is formed in the upper surface of the resist film.

Method for manufacturing semiconductor device

According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structures, first and second semiconductor pillars, first and second memory units, and a semiconductor connection portion. The stacked structures include electrode films and first inter-electrode insulating films alternately stacked in a first direction. The second stacked structure is aligned with the first stacked structure in a second direction perpendicular to the first. The first and second semiconductor pillars pierce the first and second stacked structures, respectively. The first and second memory units are provided between the electrode films and the semiconductor pillar, respectively. The semiconductor connection portion connects the first and second semiconductor pillars and includes: an end connection portion; and a first protrusion having a side face continuous with a side face of the first semiconductor pillar. The semiconductor connection portion does not include a portion smaller than a diameter of the first semiconductor pillar.

Nonvolatile semiconductor memory device and method for manufacturing the same

A semiconductor device manufacturing method includes: alternately stacking a plurality of insulating layers and electrode layers; forming a hole penetrating through a multilayer body of the insulating layers and the electrode layers; forming a conductive film on an inner wall of the hole; anisotropically etching the conductive film to selectively leave the conductive film on a sidewall of the hole; altering the conductive film into an insulator by heat treatment; and removing the insulator covering the electrode layers to expose the electrode layers into the hole.

Semiconductor device manufacturing method including exposing electrode layers into a hole

A method for manufacturing a semiconductor device, comprises forming a first film above a pattern forming material, patterning the first film to form a core material pattern, forming a second film above the pattern forming material so as to cover a side surface and an upper surface of the core material pattern, forming a third film above the second film as a protective material for the second film, etching the second and third films so that side wall sections including the second film and the third film are formed on both sides of the core material pattern and the second film and the third film of an area other than the side wall sections are removed, removing the core material pattern between the side wall sections, and transferring patterns corresponding to the side wall sections on the pattern forming material by using the side wall sections as a mask.

According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The method can include multiply stacking an insulating layer and a conductive layer alternately above a base member. The insulating layer includes silicon oxide. The conductive layer includes silicon. In addition, the method can form a SiOC film on a stacked body of the insulating layers and the conductive layers, pattern the SiOC film, and make a hole in the stacked body by etching the insulating layers and the conductive layers using the patterned SiOC film as a mask.

Method for manufacturing semiconductor device including a patterned SiOC film as a mask

A hard mask material film is formed on a semiconductor substrate and a recess is formed immediately below an opening in an upper surface of the semiconductor substrate. Next, a p-type region is formed immediately below the recess by implanting impurities into an imaging region using the hard mask material film as a mask. Moreover, a trench is formed by further processing the recess in a processing region. A half-buried dielectric film and a STI are formed by burying a dielectric material in the recess and the trench to remove the hard mask material film. Next, two electrodes are formed so as to overlap the half-buried dielectric film and the STI, respectively, and impurities are implanted into the imaging region using one electrode and the half-buried dielectric film as a mask, and hence a n-type region constituting a photodiode is formed in a region being in contact with the p-type region in the semiconductor substrate.

A method of fabricating a semiconductor device according to an embodiment includes: forming a core material on a workpiece material; forming a cover film to cover the upper and side surfaces of the core material; after forming the cover film, removing the core material; after removing the core material, removing the cover film while leaving portions thereof located on the side surfaces of the core material, so as to form sidewall spacer masks; and etching the workpiece material by using the sidewall spacer masks as a mask.

Method of fabricating semiconductor device

A nonvolatile semiconductor memory device with a substrate. A plurality of dielectric films and electrode films are alternately stacked on the substrate and have a through hole penetrating in the stacking direction. A semiconductor pillar is formed inside the through hole. A charge storage layer is provided at least between the semiconductor pillar and the electrode film. At least part of a side surface of a portion of the through hole located in the electrode film is sloped relative to the stacking direction.

Growing community of inventors

Mie-ken, Japan

Katsunori Yahashi