Fuji Electric Co., Ltd.

Fuji Electric Device Technology Co., Ltd.

Fuji Electric Systems Co. Ltd.

Fuji Electric Holdings Co., Ltd.

The Furukawa Electric Co., Ltd.

Shin-etsu Handotai Co., Ltd.

Tohoku University

Katsunori Ueno

Shinya Takashima

Masaharu Edo

Susumu Iwamoto

Tatsuhiko Fujihira

Yasuhiko Onishi

Takahiro Sato

Ryo Tanaka

Tatsuji Nagaoka

Masahito Otsuki

Yuki Ohuchi

Hideaki Matsuyama

Naoki Kumagai

Hiroyuki Yoshimura

Yasushi Miyasaka

Daisuke Kishimoto

Kenji Kunihara

Yasuhiko Ohnishi

Tadahiro Ohmi

Yuichi Harada

Koh Yoshikawa

Yoshihiro Sato

Koichi Hashimoto

Takehiko Nomura

Akinobu Teramoto

Yoshihiro Ikura

Yasukazu Seki

Masanobu Iwaya

Kiyokazu Nakagawa

Hiroshi Kambayashi

Satoshi Oka

Shusuke Kaya

Hideaki Teranishi

Shinji Ogino

Takuro Inamoto

Hiroshi Kanemaru

Akira Uedono

Tatsuo Urushidani

Reiko Hiruta

Yasumasa Watanabe

Hirotaka Suda

Ryohsuke Shimizu

Chizuru Inoue

Daisuke Mori

Kunio Mochizuki

A method for manufacturing a nitride semiconductor device including: forming N-type regions in a nitride semiconductor layer; implanting ions of an acceptor element into a region sandwiched by the N-type regions in the nitride semiconductor layer; and forming a P-type region sandwiched by the N-type regions by subjecting the nitride semiconductor layer to heat treatment and activating the acceptor element. The forming the N-type regions includes implanting ions of a donor element to the nitride semiconductor layer such that concentration of the donor element in the N-type regions is equal to or greater than concentration of the acceptor element in the P-type region. The implanting ions of the acceptor element includes implanting ions of the acceptor element such that concentration of the acceptor element in the P-type region is 1×10cmor more and 1×10cmor less.

Method for manufacturing nitride semiconductor device and nitride semiconductor device

A method for manufacturing a nitride semiconductor device including: forming an N-type region in a nitride semiconductor layer; implanting ions of an acceptor element into a region under the N-type region in the nitride semiconductor layer; and forming a first P-type region under the N-type region by subjecting the nitride semiconductor layer to heat treatment and activating the acceptor element. The forming the N-type region includes implanting ions of a donor element into the nitride semiconductor layer such that concentration of the donor element in the N-type region is equal to or greater than concentration of the acceptor element in the first P-type region. The implanting ions of the acceptor element into a region under the N-type region includes implanting ions of the acceptor element such that concentration of the acceptor element in the first P-type region is 1×10cmor more and 1×10cmor less.

A vertical MOSFET having a compound semiconductor layer is provided, the vertical MOSFET comprising a gate electrode, a gate insulating film provided between the gate electrode and the compound semiconductor layer, a drift region provided directly in contact with at least a part of the gate insulating film and being a part of the compound semiconductor layer, and a high resistance region provided at least in the drift region, is positioned below at least a part of the gate insulating film, and has a higher resistance value per unit length than that of the drift region.

Vertical MOSFET having a high resistance region

A method for manufacturing a nitride semiconductor device includes: selectively ion-implanting an element that is other than p-type impurities and n-type impurities into a first region in a first primary surface of a gallium nitride layer so as to generate crystal defects in the first region; selectively ion-implanting a p-type impurity into a second region in the gallium nitride layer, the second region being shallower than the first region in a depth direction and being within the first region in a plan view; and thermally treating said gallium nitride layer that has been ion-implanted with said element and said p-type impurity so as to thermally diffuse said p-type impurity in the second region into a third region that is within the first region and that surrounds a bottom and sides of the second region.

Nitride semiconductor device

A nitride semiconductor device is provided, comprising: a first nitride semiconductor layer of a first conductivity-type; a second nitride semiconductor layer of a second conductivity-type provided above the first nitride semiconductor layer; a junction region of a first conductivity-type which is provided to extend in a direction from a front surface of the second nitride semiconductor layer to the first nitride semiconductor layer and has a doping concentration Nequal to or higher than that of the first nitride semiconductor layer; and a source region of a first conductivity-type which is provided more shallowly than the junction region and has a doping concentration equal to or higher than the doping concentration N, wherein a dopant of the source region is an element with an atomic weight larger than that of a dopant in the junction region.

Nitride semiconductor device and method for fabricating nitride semiconductor device

To provide a nitride semiconductor device excellent in switching characteristics. A nitride semiconductor device includes: a gallium nitride layer having a first principal surface and a second principal surface located on an opposite side to the first principal surface and having a trench formed from the first principal surface to the second principal surface side; and a field effect transistor formed in the gallium nitride layer, wherein the trench has a first side surface and a second side surface inside the trench, the first side surface is a nitrogen face in the surface layer of which nitrogen atoms are located, the second side surface is a gallium face in the surface layer of which gallium atoms are located, and the field effect transistor has: a gate insulating film formed on the first side surface; and a gate electrode formed in the trench and covering the gate insulating film.

A nitride semiconductor device includes a GaN-based semiconductor layer; and an insulating film provided on a first surface of the GaN-based semiconductor layer, the insulating film containing O atoms, and other constituent atoms other than O. An interface between the GaN-based semiconductor layer and the insulating film has a terminating species which terminates a dangling bond of a Ga atom, the terminating species has an outermost electron shell in which one electron is deficient from an allowed number of outermost electrons, and is an atom or molecule having stronger bond to the Ga atom than a H atom, an amount of Ga&#x2014;O bonds is greater than an amount of bonds between the Ga atoms and the other constituent atoms.

A nitride semiconductor device includes a nitride semiconductor layer, channel cells in the nitride semiconductor layer, a source lead region of a second conductivity type in the nitride semiconductor layer, and a source electrode on a side where a first main surface of the nitride semiconductor layer is located. The channel cells each include a well region of a first conductivity type and a source region of the second conductivity type in contact with the well region. The source lead region is connected to the source region. The channel cells extend in a first direction in a planar view from a normal direction of the first main surface, and arranged in a second direction intersecting with the first direction in the planar view. The source electrode is in contact with the source lead region away from a line of the channel cells arranged in the second direction.

A gallium nitride based semiconductor device is provided, where when a thickness of a transition layer is defined as the followings, the thickness of the transition layer is less than 1.5 nm: (i) a distance between a depth position at which an atomic composition of nitrogen element constituting the gallium nitride based semiconductor layer is &#xbd; relative to that at a position on the GaN based semiconductor layer side sufficiently away from the transition layer, and a depth position at which an atomic composition of a metal element is &#xbd; of a value of a maximum if an atomic composition of the metal element constituting an insulating layer has the maximum, or a depth position at which an atomic composition of the metal element is &#xbd; relative to that at a position on the insulating layer side sufficiently away from the transition layer if not having the maximum.

Gallium nitride based semiconductor device and manufacturing method of gallium nitride based semiconductor device

The nitride semiconductor device includes: a nitride semiconductor layer; a first conductivity type source region provided on a surface of the nitride semiconductor layer; a second conductivity type well region provided in the nitride semiconductor layer and adjacent to the source region in a first direction parallel to the surface and in a second direction intersecting with the first direction; a trench located on the opposite side of the source region with the well region sandwiched therebetween in the first direction; a first conductivity type impurity region located between the well region and the trench; an insulating film provided on a bottom surface of the trench; a gate insulating film provided on the well region; and a gate electrode provided from on the insulating film to on the gate insulating film. A thickness of the insulating film is larger than a thickness of the gate insulating film.

A manufacturing method of a vertical GaN-based semiconductor device having: a GaN-based semiconductor substrate; a GaN-based semiconductor layer including a drift region having doping concentration of an n type impurity, which is lower than that of the GaN-based semiconductor substrate, and is provided on the GaN-based semiconductor substrate; and MIS structure having the GaN-based semiconductor layer, an insulating film contacting the GaN-based semiconductor layer, and a conductive portion contacting the insulating film, the method includes: implanting an n type dopant in a back surface of the GaN-based semiconductor substrate after forming of the MIS structure, and annealing the GaN-based semiconductor substrate after the implanting of the n type dopant.

Manufacturing method of vertical GaN-based semiconductor device and vertical GaN-based semiconductor device

Provided is a manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate. The manufacturing method of a semiconductor device includes forming a n-type gallium nitride layer on a gallium nitride monocrystalline substrate, and forming an impurity-implanted region that contains impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, by ion-implanting the impurities into the n-type gallium nitride layer, where the impurities include at least one type selected from among magnesium, beryllium, calcium and zinc. Here, at least part of the impurity-implanted region serves as a channel forming region of the vertical MOSFET.

Manufacturing method of semiconductor device and semiconductor device

A vertical semiconductor device is provided, including a transistor region and a Schottky diode region, and having, in a gallium nitride layer in the Schottky diode region, a first well region, a diode trench portion that is provided in direct contact with the first well region in an array direction in which the transistor region and the Schottky diode region are arrayed, a first upper drift region that is connected to the bottom of the diode trench portion, a lower drift region that is connected to the bottom of the first well region and a bottom of the first upper drift region, and a conductive portion that is connected to an upper portion of the first upper drift region.

Vertical semiconductor device and method of manufacturing vertical semiconductor device

A diode is provided, the diode including: a semiconductor layer of a first conductivity type, configured to have a trench structure and be an epitaxial layer of a wide gap semiconductor; a semiconductor layer of a second conductivity type, configured to be at least in contact with a side wall of the trench structure and be an epitaxial layer of the wide gap semiconductor; and an electrode configured to be in contact with the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type, on the semiconductor layer of the first conductivity type and the semiconductor layer of the second conductivity type.

Diode and method of manufacturing diode

Provided is a semiconductor device including at least two isolation trench portions; a mesa region that is provided between the at least two isolation trench portions and includes a source region having a first conduction type, a base region having a second conduction type and at least a portion thereof provided below the source region, and a gate trench portion; and a contact layer that is an epitaxial layer provided at least in contact with side portions of the mesa region and bottom portions of the isolation trench portions positioned lower than the gate trench portion, and having a second-conduction-type impurity concentration higher than that of the base region, wherein the same impurities as in the contact layer are present in the source region, or the contact layer is provided higher than the source region.

Semiconductor device and manufacturing method of semiconductor device

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Matsumoto, Japan

Katsunori Ueno