Sony Corporation

Other

Sony Electronics Inc

Sony Coorporation

Katsunori Seno

Kurt T Knorpp

Lee-Lean Shu

Takahiro Seki

Tomotaka Miyashiro

Naotaka Osawa

Tetsuo Kondo

Hiroshi Sato

Akihiko Hashiguchi

There is provided a projection device including a projecting unit that projects an image onto a screen, an acquiring unit that acquires image data of the image to be projected onto the screen, a generating unit that generates first pixel data representing pixels of first spot beams to be projected onto the screen without overlapping with each other among a plurality of spot beams to be projected at different timings based on the image data, and a driving control unit that controls driving of the projecting unit based on the first pixel data in a manner that the first spot beams are projected onto the screen as pixels of the image data.

Projection device, projection method, program, and electronic device

There is provided an image output device including a projectable region calculating unit that calculates a projectable region which is a region on a screen in which laser beam is projectable based on a trajectory in which scanning with the laser beam is performed using information specifying the screen onto which an image is projected by two-dimensional scanning with the laser beam, a projection window setting unit that causes the laser beam to be emitted and sets a projection window serving as a range in which the image is projected in the projectable region, and a generating unit that generates a pixel value of each of positions corresponding to pixels included in the image within the projection window on the screen for each pixel in a manner that the image is projected in the range set by the projection window.

Image output device, image output method, and program

A power supply voltage control apparatus including an input signal generation circuit of wide uses or a small-sized monitor circuit of a novel configuration, and a semiconductor circuit and a method for driving the same, having a semiconductor circuit, an input signal generation circuitable to change the phase difference i of a reference signal out&#x3c6;i and an input signal out&#x3c6;in accordance with a control signal Si when generating the two signals from a clock, a monitor circuithaving a characteristic between a power supply voltage and delay the same as that of a critical path of the semiconductor circuit, propagating the input signal out&#x3c6;, and outputting a delayed signal out&#x3c6;' to be delayed exactly by a time equivalent to a delay of the critical path (or smaller by a constant ratio), a delay detection circuitfor detecting a delay of the delayed signal out&#x3c6;&#x2032; relative to the reference signal out&#x3c6;i, and a power supply voltage control circuitfor controlling a power supply voltage Vsupplied to the semiconductor deviceand the monitor circuitbased on the detection result.

Power supply control device, semiconductor device and method of driving semiconductor device

A semiconductor device provided with a replica circuit functioning as an equivalent circuit to that of a path configuration selected as a critical path in the semiconductor circuit and an adjustable delay device for example between an output side of the replica circuit and a phase comparator, the delay value of the delay device being adjustable after production of the chip to a value enabling the replica system including the replica circuit to reliably operate with a margin from the critical path delay of the semiconductor circuit, whereby it becomes possible to prevent setting of an excessive margin and becomes possible to increase the margin when the margin ends up smaller than expected and therefore it becomes possible to flexibly and efficiently configure the replica circuit, and a method of constitution of the same.

Semiconductor device replica circuit for monitoring critical path and construction method of the same

A power source voltage controller which can set the optimal margin for a replica circuit and shorten the time for the power source voltage to converge to the optimal value, having a replica circuit for monitoring a delay time of a critical path by propagating a reference signal having a power source voltage-delay characteristic approximately equivalent to a critical path in a semiconductor circuit, a phase difference detection circuit and an encoder receiving a delay signal by the replica circuit and the reference signal and detecting the phase difference of the delay signal from the reference signal and outputting the detection result as phase difference information, voltage control circuits for generating a power source voltage of a value based on a phase difference information signal and supplying it to the semiconductor circuit and the replica circuit, and a delay error correction circuit arranged at the input side of the reference signal of the replica circuit and correcting the delay difference with the critical path.

Power source voltage controller

A current sensing, cascadable differential amplifier has a special bias circuit that provides a low impedance input and a high impedance output, whereby plural stages may be connected in cascade. Optionally, active current sources are used as pull-ups for the data lines, to increase the output impedance and improve the data line common mode level. The amplifier performs as a current sensing sense amplifier in a large scale, fast access semiconductor means and in this application, the memory does not need equalizing clock signals, nor is the access time slowed materially in the plural cascade stages.

SRAM with current-mode test read data path

A semiconductor circuit capable of keeping the leakage current to a minimum while drawing out the effect of improvement of speed due to the lowering of the threshold voltage to a maximum, wherein delay paths to which low threshold voltage gate elements are applied are restricted to delay paths in a range from a maximum delay value before a lowering of a threshold voltage (at a higher speed than this) to a new maximum delay value in a case where low threshold voltage gate elements are applied to this (at a lower speed than this), whereby a leakage current due to low threshold voltage transistors can be kept to the minimum while drawing out the effect of improvement of speed due to the lowering of the threshold voltage to the maximum, thereby solving the problem of an unrequired leakage current applied to a chip over a wide range.

Semiconductor circuit

A semiconductor memory device including a plurality of memory cells arranged in a matrix; a plurality of bit lines; and a plurality of word lines controlled by column addresses for the same row addresses of the memory cells, wherein memory cells belonging to the same row are operatively connected to the bit lines by the plurality of word lines having the same row address and different column addresses.

Semiconductor memory activated by plurality of word lines on same row

Clock signals of the same phase are formed even when signal delays occur in clock signals transmitted on a clock line. In a clock synchronizing circuit which synchronizes circuit elements using clock signals taken from a common clock line, the clock line is bent midway into a pair of clock lines, and a center phase signal generating means generates a clock signal having a phase which is in the center of two clock signals of differing phase obtained from arbitrary points on the pair of clock lines which are at equal distances from the point at which the clock line is bent over. By using pairs of clock signals of differing phases taken at equal distances from the bend over point, three clock signals all having equal phase are obtained.

Clock synchronizing circuit

A test circuit for a single chip semiconductor memory array, located in the chip, enables testing of all columns along a word lines without additional column readout circuits. A pair of current detecting differential amplifiers are connected to the bit lines of multiple memory cells along a word line, and the amplifier outputs are compared to generate a pass/fail signal during a read access.

Current mode test circuit for SRAM

A current sensing, cascadable differential amplifier has a special bias circuit that provides a low impedance input and a high impedance output, whereby plural stages may be connected in cascade. Optionally, active current sources are used as pull-ups for the data lines, to increase the output impedance and improve the data line common mode level. The amplifier performs as a current sensing sense amplifier in a large scale, fast access semiconductor memory and in this application, the memory does not need equalizing clock signals, nor is the access time slowed materially in the plural cascade stages.

SRAM with current-mode read data path

In a single chip semiconductor memory, having independent memory areas for normal memory cells and redundant memory cells, the redundant cells are tested in a parallel or multi-bit test mode simultaneously with the normal cells they replace, by enabling the redundant memory area in response to simultaneous detection of the state of the multi-bit test mode, the presence of a programmed redundant bit for a memory cell under test, and the operative selection of the normal memory matrix.

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Kanagawa, Japan

Katsunori Seno