Hitachi-high-technologies Corporation

Hitachi, Ltd.

Elpida Memory, Inc.

Renesas Technology Corp.

Hitachi High-tech Corporation

Opnext Japan, Inc.

Katsunori Hirano

Tadanobu Toba

Yuji Sonoda

Shuji Kikuchi

Yuichi Sakurai

Masashi Watanabe

Shigeru Kawamata

Yoshinobu Hoshino

Masahiro Ohashi

Masato Kamio

Masashi Wada

Mitsuaki Katagiri

Atsushi Hasegawa

Hideki Osaka

Keiichi Yamamoto

Wen Zheng Li

Ichiro Anjo

Takeshi Wada

Norio Chujo

Takeshi Yamashita

Tetsuya Aoki

Takayuki Nakao

Akio Osaki

Masayuki Takahashi

Tomoaki Shimotsu

Takashi Kanesaka

Ken Iizumi

There is provided a charged particle beam device which includes a charged particle beam source, a charged particle beam optical system that irradiates a sample with a charged particle beam from the charged particle beam source, a detector that detects a secondary signal generated from the sample by irradiation with the charged particle beam, and an image processing unit that executes integration processing of image data obtained from the secondary signal and outputting an integrated image, and in which the image processing unit executes a normalization integration computation of outputting an integrated image in which a luminance value of the integrated image is always '1' in an integration process.

Charged particle beam device and image processing method in charged particle beam device

Provided is a data processing device with which, when a temporary network congestion occurs, it is possible to avoid a buffer overflow and sustain a process. When a request for retransmission of the same data with respect to a processor element from a buffer occurs continuously a prescribed number of iterations, a data processing device according to the present invention determines that it is possible that a buffer overflow occurs, and suppresses an increase in the volume of data which is accumulated in the buffer (see FIG.).

Data processing device, semiconductor external view inspection device, and data volume increase alleviation method

A scan control unit for generating two-dimensional coordinates for performing a scan with an electron beam of an electron scanning microscope is provided with first and second transforming units for transforming coordinates in the horizontal (X) direction and the vertical (V) direction. An area to be tested in a sample is scanned with an electron beam in an arbitrary direction. As the first and second transforming units, small-capacity transformation tables (LUTs) capable of operating at high speed in each of the horizontal (X) direction and the vertical (Y) direction are used. By also using a large-capacity transformation table (LUT) that stores coordinate transformation data corresponding to plural scan types, a test apparatus compatible with the plural scan types, having multiple functions, and capable of performing high-speed scan control is realized.

Test apparatus

In a circuit board on which a plurality of CPUs are mounted, the CPUs comprises: monitor units for outputting task statuses of the respective CPUs; and a diagnosis circuit connected to the plurality of CPUs, comparing and judging combinations of the task statuses of the plurality of CPUs based on information on task statuses outputted from the monitor units, and detecting false operations and failures of the circuit board.

Method of diagnosing circuit board, circuit board, and CPU unit

The present invention relates to a DRAM stacked packages, a DIMM, a method for testing them, and a semiconductor manufacturing method. According to the present invention, there is provided a DRAM stacked package comprising: a plurality of stacked DRAMs; external terminals to which test equipment is connected, said external terminals being used to input/output at least address, command, and data; and an interface chip provided between said plurality of stacked DRAMs and said external terminals. The plurality of DRAMs and the interface chip are implemented on a package. The interface chip comprises: a test circuit including: an algorithmic pattern generator for generating a test pattern used to test the plurality of DRAMs; applying circuits for applying said generated test pattern to the plurality of DRAMs; and a comparator for comparing each response signal received from the plurality of DRAMs with an expected value for judgment.

DRAM stacked package, DIMM, and semiconductor manufacturing method

Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from tho algorithmic pattern generator; a fail address acquisition part for storing an address of the memory under test (fail address) when a result compared by the comparator is failed; a fail address analysis part for analyzing the failed address and calculating the address to be repaired (repair address); and a cycle-pattern generator for redundancy processing for inserting the address to be repaired into a test pattern and applying the address to the memory under test, so that even when capacity of the semiconductor memory is increased, a fabrication yield thereof is raised by testing the memory after the packaging and by performing the redundancy processing of a defective.

Semiconductor testing equipment, testing method for semiconductor, fabrication method of semiconductor, and semiconductor memory

A signature circuit, i.e., a random-number generating circuit, is provided in a memory test apparatus. Also, a signature circuit is provided in each of devices-under-test. This configuration allows the large number of semiconductor integrated-circuit devices to be tested at one time with a high efficiency. This condition realizes a tremendous reduction in the test cost.

Semiconductor device, and the method of testing or making of the semiconductor device

A sample & hold type phase detector is used in a CDR IC and, in jitter transfer bandwidth adjustment, VCO output waveforms 90&#xb0; out of phase with each other can be inputted to the phase detector, whereby a jitter transfer bandwidth can be calculated by only the measurement of frequency and of a DC voltage and it is possible to make a jitter transfer bandwidth adjustment in DC test for IC.

Optical modules and methods of making the optical modules

Growing community of inventors

Yokohama, Japan

Katsunori Hirano