The Kansai Electric Power Co., Inc.

Central Research Institute of Electric Power Industry

Other

National Institute of Advanced Industrial Science and Technology

Nissin Electric Co., Ltd.

The Kansai Electric Co., Inc.

Central Research Institution of Electrical Power Industry

Katsunori Asano

Yoshitaka Sugawara

Hidekazu Tsuchida

Koji Nakayama

Isaho Kamata

Toshiyuki Miyanagi

Tomonori Nakamura

Kazutoshi Kojima

Tetsuya Miyazawa

Yoshifumi Minowa

Shiyang Ji

Mitsuru Matsukawa

Toshihiko Shikata

Tetsuro Hemmi

The present invention provides a semiconductor structure which includes at least a p-type silicon carbide single crystal layer having an &#x3b1;-type crystal structure, containing aluminum at impurity concentration of 1&#xd7;10cmor higher, and having thickness of 50 &#x3bc;m or greater. Further provided is a method for producing the semiconductor structure of the present invention which method includes at least epitaxial growth step of introducing silicon carbide source and aluminum source and epitaxially growing p-type silicon carbide single crystal layer over a base layer made of silicon carbide single crystal having &#x3b1;-type crystal structure, wherein the epitaxial growth step is performed at temperature conditions of from 1,500&#xb0; C. to 1,700&#xb0; C., and pressure conditions of from 5&#xd7;10Pa to 25&#xd7;10Pa.

Semiconductor structure, semiconductor device, and method for producing semiconductor structure

With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle &#x3b8; of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 &#x3bc;m/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

Silicon carbide semiconductor device and manufacturing method therefor

SiC-IGBTs, which have an inversion-type channel with high channel resistance and have high on-voltage due to an influence from the surface state of the interface between a gate insulating film and a base layer, are required to decrease the on-voltage. An embedded collector region is partially formed in a base layer which is formed on an emitter layer of a SiC semiconductor. A channel layer is formed on the base layer and the embedded collector region to constitute an accumulation-type channel. Consequently, at on time, holes are accumulated in the upper layer portion of the channel layer so that a low-resistant channel is formed. Current by the holes flows to the emitter layer through a channel from the collector region and becomes a base current for an npn transistor composed of the embedded collector region, the base region and the emitter region.

Voltage-controlled semiconductor device

A problem to be solved by the present invention is to eliminate variation in potential in a turn-off time period of each GTO element, and to stabilize a gate drawing current by surely performing the turn-off of the GTO element. In an inverter apparatus having a three-phase inverter configured to include paired GTO elements an inverter control portion has a simultaneous switching prevention function of delaying a turn-on operation of each of the GTO elements which correspond to phases other than a phase corresponding to an optional one of the GTO elements and also correspond to an electrode opposite to an electrode corresponding to the optional one of the GTO elements by a predetermined time in a case where a turn-on command signal for turning on each of the GTO elements is generated within a predetermined time period since the turn-off of the optional one of the GTO elements.

Inverter apparatus comprising switching elements

A buried gate region, a buried gate contact region and a gate contact region are provided on an SiC substrate. Thereby, a depletion layer expands in the channel region, and a high withstand voltage is attained in the normally off state. By applying a voltage of the built-in voltage or less to a gate, the depletion layer in the channel region becomes narrower and an ON-state resistance becomes low. Furthermore, when a voltage of the built-in voltage or more is applied to the gate, holes are injected from the gate so as to cause the conductivity modulation, and the ON-state resistance becomes further low.

Vertical field-effect semiconductor device with buried gate region

Insulated gate semiconductor device

Growing community of inventors

Osaka, Japan

Katsunori Asano