Sharp Kabushiki Kaisha Corporation

Katsunobu Mori

Hiroyuki Nakanishi

Toshiya Ishio

Shinji Suminoe

Yoshihide Iwazaki

Yasunori Chikawa

Takamichi Maeda

Naoyuki Tajima

Takaaki Tsuda

Yoshiaki Honda

Katsuyuki Tarui

Mitsuaki Osono

Masao Hayakawa

Shigeyuki Sasaki

Tomoyo Maruyama

Takamasa Tanaka

A manufacturing method of a semiconductor device, comprising the steps of forming an insulation layer, which has an opening section in an area including an area on an electrode pad, on a top surface of the semiconductor substrate on which the electrode pad is formed; at least forming a first barrier metal layer, which becomes a part of a leading wiring layer, in an inner peripheral surface of the opening section including the top surface of the electrode pad; at least forming a main conductor layer, which becomes a part of the leading wiring layer, in an area surrounded by the first barrier metal layer in the opening section; eliminating an upper portion of the main conductor layer at least to a position at which the first barrier metal layer is exposed, and forming a second barrier metal layer, which becomes a part of the leading wiring layer, so as to cover the whole top surface of the main conductor layer.

Semiconductor device having a leading wiring layer

A leading wiring layer is provided with a main conductor layer, a first barrier metal layer for covering bottom and side surfaces of the main conductor layer, and a second barrier metal layer for covering a top surface of the main conductor layer. This ensures the respective barrier metal layers to cover entire surroundings including the side, bottom and top surfaces of the main conductor layer.

A semiconductor device includes (i) spacers between a first electronic component and a second electronic component facing each other, for keeping a distance between the first and second electronic components constant and (ii) combining parts for combining the first electronic component with the second electronic component. The spacers are made of liquid resin material made of thermosetting resin, and the combining parts are made of liquid conductive combining material including metal and thermosetting resin. A manufacturing method of the semiconductor device includes the steps of: forming the spacers on first electrode pads by hardening the liquid resin material; providing the liquid conductive combining material on either the first electrode pads or second electrode pads; aligning the first electronic component with the second electronic component so that (i) the spacers contact with the second electrode pads and (ii) the liquid conductive combining material contact with either at least a part of one the first electrode pads or at least part of one of the second electrode pads; and combining the first electronic component with the second electronic component by hardening the liquid conductive combining material. The steps above are carried out in this order.

Semiconductor device in which a plurality of electronic components are combined with each other

An integrated semiconductor circuit includes a semiconductor chip on which surface a plurality of connection electrodes are formed, a lower insulating layer covering the surface of the semiconductor chip such that the connection electrodes are exposed, a plurality of wiring portions formed on the lower insulating layer, each of the wiring portions being connected to the connection electrode at one end and provided with a component connection portion at the other end, an upper insulating layer covering the wiring portions such that the component connection portions are exposed, and an electronic component connected between different component connection portions.

Integrated semiconductor circuit including electronic component connected between different component connection portions

A semiconductor chip of the present invention is so arranged that a front face on which an element circuit is formed has electrode pads and a side face and a back face are coated with a shielding layer for shielding electromagnetic waves. With this, it is possible to provide a semiconductor element capable of being easily manufactured into a smaller semiconductor device compared with a conventional semiconductor device equipped with a shielding cap; a semiconductor device; and a method for manufacturing a semiconductor element.

Semiconductor element with electromagnetic shielding layer on back/side face(s) thereof

A manufacturing method of a semiconductor device for providing wires on a front surface of a semiconductor wafer by providing a plating layer, in which conductive layers provided on the front and back surfaces of the semiconductor wafer are electrically conducted by solder filled in its through-holes, and electrolytic plating is carried out by electrically connecting cathode terminals of an electrolytic plating apparatus and the conductive layer provided on the back surface of the semiconductor wafer which is provided with a mask on the conductive layer provided on its front surface.

Manufacturing method of semiconductor device

In order to simplify a providing method of a wiring that electrically connects a semiconductor integrated circuit to a substrate, the semiconductor integrated circuit that is covered with an insulating layer except for an electrode area having an electrode pad is fixed on a formation side of the substrate having a terminal connected to the semiconductor integrated circuit so that the electrode pad is exposed. Next, a metallic thin film is provided on a wiring area on which a wiring for electrically connecting the electrode pad to the terminal is provided. Further, the wiring is provided on the metallic film of the wiring area in accordance with plating.

Semiconductor device with plating wiring connecting IC electrode pad to terminal

The present invention provides a quality and reliable high-density package (Chip Size Package) semiconductor device without problems related to the manufacturing process. The semiconductor device includes the first semiconductor substrate piece having electrode pads formed on its principle surface, and a second semiconductor mounting piece mounted thereon via a first insulating film and a die-attaching material. On the surface opposite the first semiconductor substrate piece of the second semiconductor substrate piece, formed are wiring patterns and a second insulating film for protecting the wiring patterns. The wiring patterns include electrode pads, wires, and lands where external connection terminals are provided.

Semiconductor device and method of manufacturing same

A semiconductor integrated circuit device in accordance with the present invention is provided with first electrode pads, a first insulation layer and a second insulation layer. The first electrode pad are formed on the circuit formation face side of an IC chip. The first insulation layer is placed on areas other than the upper portions of the first electrode pads. The second insulation layer, which is made from a photosensitive material, is formed on the first insulation layer with an opening section for allowing at least one portion of the first electrode, the wire and at least one portion of the second electrode to be exposed. Here, the wire and the second electrode are formed by filling the opening section of the second insulation layer with particles of a conductive material. Thus, it is possible to provide a semiconductor integrated circuit device to which a fine wire processing technique is applied while maintaining the same functions as conventional devices at low costs, and a manufacturing method for such a device.

Semiconductor integrated circuit device and manufacturing method thereof

A method of manufacturing a semiconductor device including two semiconductor chips having mutually different element forming face areas on respective surfaces of a die pad of a lead frame prepared by sealing the semiconductor chips with resin by setting the lead frame in a resin sealing use mold having an injection gate for injecting therethrough a sealing resin, includes the steps of: (a) mounting the semiconductor chips on respective surfaces of the die pad in such a manner that when setting the lead frame in the resin sealing use mold, a distance between a side face of the semiconductor chip having a larger element forming face area on the injection gate side and a side face of the semiconductor chip having a smaller element forming face area on the injection gate side becomes shorter than a distance when these semiconductor chips are mounted at a center on respective surfaces of the die pad; (b) setting the lead frame in the resin sealing use mold so that the above side faces of the semiconductor chips are positioned on the injection gate side; and (c) injecting the sealing resin from the injection gate.

Semiconductor device sealed with a sealing resin and including structure

An insulation material and a wire pattern are provided on at least one of the surfaces of a die pad. Wires of the wire pattern are patterned in such a manner that at least one inner lead included in at least one of two lead groups is electrically connected to an electrode pad provided on the element forming surface of the semiconductor chip near the side edge other than the side edge opposing the lead group including the above particular inner lead, while at least one inner lead included in the other lead group is electrically connected to an electrode pad provided on the element forming surface of the semiconductor chip near the side edge other than the side edge opposing the other lead group. Accordingly, a multichip-1-package semiconductor device using any kind of semiconductor chip can be realized. Also, the costs of the semiconductor device are saved and the semiconductor device can be developed in a shorter period by omitting the design modification of the semiconductor chip.

Semiconductor device including a wire pattern for relaying connection

In a TCP (tape carrier package) semiconductor device having opposing, inner lead arrays bonded to a semiconductor device, a projection or projections are provided on each of the inner leads disposed at intervals of a greater distance on one side of the semiconductor, within a range for allowing the resin to flow out.

Tape carrier package semiconductor device

A semiconductor device comprising a semiconductor chip, a plurality of electrode pads formed on the semiconductor chip, a metal wiring having a desired pattern and connected to the electrode pads, an anisotropic conductive film containing fine conductive particles and laminated on the semiconductor chip including the metal wiring, and an external electrode, in which the anisotropic conductive film has a concave portion at a desired portion on the metal wiring and the metal wiring is connected to the external electrode through the intermediary of the fine conductive particles present in the anisotropic conductive film by stuffing and sticking the external electrode in the concave portion.

Semiconductor device having external electrodes formed in concave

In a semiconductor device of a tape carrier package type, the gap width between inner leads connected with a first edge side of a semiconductor chip set within a device mounting hole provided in the tape carrier is larger than the gap width between leads connected with a second edge side opposite to the first edge side of the semiconductor chip, and the gap length of device mounting hole between the first edge of the semiconductor chip and the first edge of the device mounting hole corresponding to the first edge of the semiconductor chip is smaller than the gap length between the second edge of the semiconductor chip and the second edge of the device mounting hole corresponding to the second edge of the semiconductor chip. Such structure enables an encapsulation resin to fill uniformly the device mounting hole, and the encapsulation resin after encapsulation has a shape of a designed dimension.

Tape carrier semiconductor device

A tape carrier semiconductor device has a resin sealed area not so larger than the size of the semiconductor chip, e.g. substantially not exceeding 2 mm to the outside. A device hole is not larger than an area formed by extending the outer periphery of the semiconductor chip to the outside by 0.3 mm and an epoxy resin of 500-1200 ps in viscosity is used for sealing the chip.

Growing community of inventors

Nara, Japan

Katsunobu Mori