Texas Instruments Corporation

Katsunobu Hirakawa

Jay Bryan Reimer

Weifeng Joe Zhou

A data processor timer comprising a writeable control register, a look-up table and a loadable counter. The loadable counter operates in a first mode to load the count data field and operates in a second mode an entry from said look-up table specified by the count data field. The loadable counter generating a time out signal upon counting a number of clock pulses equal to said count. The writeable control register preferably includes a mode bit selecting the first or second modes. This invention is suitable for a pre-scalar counter as part of a data processor watchdog timer.

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Ibaraki, Japan

Katsunobu Hirakawa