Renesas Electronics Corporation

Nec Electronics Corporation

Katsumi Togawa

Taro Fujii

Takao Toi

Teruhito Tanaka

Kenichiro Anjo

Yoshitaka Izawa

Ryoko Sasaki

Masato Motomura

A semiconductor device includes a data path having a plurality of processor elements, a state transition management unit managing a state of the data path, and a parallel computing unit in which an input and an output of data is sequentially carried out, and an output of the parallel computing unit is capable of being handled by the plurality of processor elements.

Semiconductor device including array of processor elements and method of controlling the same

A semiconductor device includes: a local memory outputting a plurality of pieces of weight data in parallel; a plurality of product-sum operation units corresponding to the plurality of pieces of weight data; and a plurality of unit selectors corresponding to the product-sum operations units, supplied with a plurality of pieces of input data in parallel, selecting the one piece of input data from the supplied plurality of pieces of input data according to a plurality of pieces of additional information each indicating a position of the input data to be calculated with the corresponding product-sum arithmetic unit calculator in the pieces of input data, and outputting the selected input data. Each of the plurality of product-sum arithmetic units performs a product-sum operation between the weight data different from each other in the plurality of pieces of weight data and the input data outputted from the corresponding unit selector.

Semiconductor device, data generation methods used for the same, and method of controlling the same

A semiconductor device includes a dynamic reconfiguration processor that performs data processing for input data sequentially input and outputs the results of data processing sequentially as output data, an accelerator including a parallel arithmetic part that performs arithmetic operation in parallel between the output data from the dynamic reconfiguration processor and each of a plurality of predetermined data, and a data transfer unit that selects the plurality of arithmetic operation results by the accelerator in order and outputs them to the dynamic reconfiguration processor.

Semiconductor device and method of controlling the semiconductor device

A semiconductor device and method includes a configuration information storage memory that stores a plurality of configuration information items, a state transition management unit that selects any one of the plurality of configuration information items, and a data path unit that dynamically reconfigures a circuit according to the configuration information item selected by the state transition management unit. When a detection of a failure or no failure is made in any one of a plurality of logic circuit groups provided in the data path unit, the state transition management unit selects the configuration information item depending on a result of the detection.

Semiconductor device and control method thereof for processing

According to an embodiment, a reconfigurable deviceincludes a configuration information storage memory, a state transition management unit, and a data path unit. When a failure is not detected in either of tiles Tand Tprovided in the data path unit, the state transition management unitselects the configuration information item so that a first processing circuit is configured using the tiles Tand T, while when a failure is detected in the tile T, the state transition management unitselects the configuration information item so that after a first intermediate processing circuit is configured using the tile Tin which no failure is detected, a second intermediate processing circuit is configured again using the tile Tin order to achieve the first processing circuit.

An array type processor comprises a data path unit to execute processing, and a state management unit to control the state of the data path unit in accordance with a command that specifies processing on the data. An input DMA circuit reads from a memory information and data to be processed including a command corresponding to the data. The input DMA circuit first transfers the command to the state management unit, and then transfers the data to be processed to the data path unit.

Stream processor and information processing apparatus

A descriptor queue composed of descriptors containing input address information that represents an address for storing data to be processed and output address information that represents an address for storing processed data is constructed and stored in a memory. A stream processor for performing a plurality of processes parallel to each other on the data to be processed acquires a descriptor from the memory, reads data to be processed from the memory according to the input address information contained in the descriptor, processes the data, and stores the processed data back into the memory according to the output address information contained in the descriptor.

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Tokyo, Japan

Katsumi Togawa