Hitachi, Ltd.

Hitachi Video Eng. Inc.

Katsumi Takeda

Akio Yamamoto

Takashi Furuhata

Yasuhiro Inagami

Hiroaki Takahashi

Kiyoshi Ogawa

Hiroaki Fujii

Hidenori Umeno

Kanji Kubo

Nobuo Azuma

Tadashi Saitoh

Hideo Wada

Jun Yamada

Yoshizumi Watatani

Takashi Takeuchi

Shigeyuki Sudo

Yasuaki Takahara

Akira Yamaoka

Shunji Tanaka

Masashi Mori

Junichi Iida

Masatoshi Haraguchi

Toshihiro Matsunaga

Masahiro Kitano

Yoshitaka Ohfusa

Hiroyuki Okura

Keiji Saijo

Satoshi Seino

Keiichi Sasaki

Katsuya Kohda

A data processing unit which can access a greater number of registers than registers addressable by an instruction to realize high-speed execution of a program. To this end, the data processing unit includes a greater number of floating point registers than the number of registers addressable by an ordinary instruction, a window start pointer register, a window start pointer valid register, a conversion circuit, when the window start pointer valid register has a value of 1, for converting a floating point register number in the instruction to a physical floating point register number and for changing a conversion pattern depending on the value of the window start pointer register, a window start pointer set instruction for setting a value at the window start pointer register, and floating point register pre-load and post-store instructions having a register field different in length from the ordinary instruction, and wherein the floating point register number specified by the register field is converted by the conversion circuit to the physical floating point register number on the basis of the value of the window start pointer register.

Data processing unit

The number of oscillators required to construct a digital radiocommunication terminal can be reduced and a circuit used for the digital radiocommunication terminal can be reduced in size. For this purpose, the digital radiocommunication terminal for effecting information transmission using an N (integer)-phase-shift-keyed signal (identification symbol number N=4 upon .pi./4 shifted QPSK modulation), is constructed such that an oscillation frequency generated from a reference oscillator employed with a frequency synthesizer is selected to have a common multiple of a second intermediate frequency and an identification symbol phase N and is supplied to a detector for outputting received data therefrom.

Digital radiocommunication terminal

The data processing unit includes a greater number of physical floating point registers than the number of floating point registers accessible by an instruction, window start point register having a plurality of bits, 1-bit window start pointer valid register, conversion apparatus for converting a floating point register number in an instruction to a physical floating point register number when the value of the window start pointer valid register is 1, and changing the pattern of this conversion by a value obtained from the value of the window start pointer register or the value of a window stride designated in a specific instruction, and the value of the window start pointer register. Also provided is an instruction controller for detecting a window start pointer set instruction for setting a value to the window start pointer register, a floating point register pre-load instruction for converting the floating point register number in the instruction to a physical floating point register number by the conversion circuit from the value obtained from the value of the window start pointer register and the value of the window stride, and storing a main memory data in the physical floating point register indicated by the physical floating point register number.

Data processing unit which can access more registers than the registers

A magnetic recording apparatus of the rotary head helical scan type which can selectively record input information signals of a plurality of signal formats includes an input signal kind discriminating circuit, a controller for generating control output signals to set each section of the magnetic recording apparatus into a predetermined mode on the basis of a recording mode command, a recording signal processing circuit which is respectively switched to a predetermined mode in accordance with an output signal of the controller, and a servo control circuit, wherein there is an effect such that one magnetic recording apparatus can automatically record the input signals of a plurality of formats such as an NTSC signal, an HD signal, and the like in the optimum mode by a simple and easy to use method.

Magnetic recording apparatus with capability of recording signals of a

An information processing system comprises: plural processors; a shared memory connected to the plurality of processors for enabling communication between the processors; a unit disposed in the shared memory for storing information for specifying a processor connected thereto; and a unit for checking, when a first processor communicates with a second processor, whether or not the first and second processors are connected to the shared memory for direct access thereto by referring to the information storing means. A method of communication between processors used with a multiprocessor system, comprises the steps of: storing information for specifying a processor connected to the shared memory for direct access thereto in a predetermined register of the shared memory; feeding a communication instruction for instructing a first processor to communicate with a second processor via the shared memory; checking, in response to the communication instruction, whether or not the first and second processors are connected to the shared memory to enable direct access; storing communication information from the first processor in the shared memory, in response to confirmation that the first and second processors are connected to the shared memory; feeding a communication read interruption from the shared memory to the second processor; and reading out, in response to the communication read interruption, the communication information from the shared memory to feed the communication information to the second processor.

Multi-processor system having shared memory for storing the

Virtual machine system having an extended storage

An audio signal recording and playback apparatus of a magnetic recording and playback apparatus operates to record and play back multiple audio signals together with a video signal in first and second recording areas formed in correspondence to audio signals of first and second sets each consisting of two channels. Among input stereo audio signals in four channels at most, two-channel signals corresponding to left and right side information are recorded as main audio signals in the first recording area and remaining two-channel signals are recorded selectively as ancillary audio signals in the second record area.

Audio signal recording and playback apparatus of magnetic recording and

In a computer system capable of being configured in a multiprocessor system, a plurality of virtual machines are grouped by object of use to define a plurality of processor groups. Each processor has an identifier for a processor group to which it belongs. When an instruction which requires synchronous execution among the processors is executed, the processor identifies the processor group to which it belongs and requests the synchronous execution of the instruction to only the processors in the group. In another aspect, each processor which has a request for execution refers to its own identifier to determine if the request is from a processor of the same group in order to determine whether it should execute the instruction or not. When the processor completes the execution of the instruction, it sends an end signal to the requesting processor so that another instruction from other processors in the same group can be executed.

Multiprocessor system statically dividing processors into groups

In an apparatus for tracking an optical disc, speed in acquiring a steady tracking condition is significant. That is, if the light beam is subjected to feedback while it is positioned in a positive feedback region, e.g., in the middle of adjoining tracks, the track servo system causes an oscillation. Therefore, according to the present invention, there is effected a comparison between the magnitude of signals from two pits disposed offset from the track and a pit on the track to determine the position of the light beam so that the tracking error signal may be inversed when the light beam is positioned in the middle of adjoining tracks. This will operate the tracking system in the negative feedback region to more quickly achieve a stable tracking state.

Apparatus for tracking an optical disc

An optical recording and reproducing system having an accurate high-speed optical head positioning apparatus. In one embodiment, a positive acceleration is applied to the optical head until the optical head has moved half the distance to a target track. Thereafter, a negative acceleration is applied to the optical head to decelerate the optical head until the optical head arrives at the target track. Feedback control is not used while the optical head is moving, thus eliminating a delay in response time due to a limited servo band upon the transition from the positive acceleration to the negative acceleration.

Optical recording and reproducing system having an accurate high-speed

In a storage system having a main storage and a buffer storage accessable by a plurality of requesters, the buffer storage comprises a buffer storage data area having a plurality of storage areas for storing a portion of data of the main storage as a copy of the main storage for each predetermind storage unit, and a buffer storage addess area for storing addresses of the predetermined storage units coresponding to the storage areas. The buffer storage address area is divided into a plurality of addres area banks each interleaved by storage unit, and the buffer storage data area is divided into a plurality of data area banks each interleaved by an access width unit.

Storage system

In a storage system having a main storage and a buffer storage accessable by a plurality of requesters, the buffer storage comprises a buffer storage data area having a plurality of storage areas for storing a portion of data of the main storage as a copy of the main storage for each predetermined storage unit, and a buffer storage address area for storing addresses of the predetermined storage units corresponding to the storage areas. The buffer storage address area is divided into a plurality of address area banks each interleaved by storage unit, and the buffer storage data area is divided into a plurality of data area banks each interleaved by an access width unit.

Growing community of inventors

Hadano, Japan

Katsumi Takeda