Sharp Kabushiki Kaisha Corporation

Katsumi Sawai

Yasuo Torimaru

A row decoder for a semiconductor memory device is disclosed. The row decoder comprises: CMOS NAND circuits each having P-channel transistors and N-channel transistors; and CMOS NOR circuits which follow the NAND circuits and have P-channel transistors and one or more N-channel transistors. The ratio of the channel length to the channel width of the P-channel transistors of the NAND circuits is greater than that of the N-channel transistors of the NAND circuits. And, the ratio of the channel length to the channel width of the N-channel transistors of the NOR circuits is greater than that of the P-channel transistors of the NOR circuits.

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Tenri, Japan

Katsumi Sawai