Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Corporation

Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

The University of Tokyo

Sumitomo Metal Industries, Inc.

Kureha Kagaku Kogyo Kabushiki Kaisha

Kyushu Institute of Technology

Tokyo Kikai Seisakusho, Ltd.

Sumikin Chemical Co., Ltd.

Katsumi Satoh

Noritoshi Hirano

Kazuhiro Morishita

Yoshihiro Yamaguchi

Futoshi Tokunoh

Shinji Koga

Tomoko Matsudai

Toshinobu Kawamura

Kiyoshi Takeuchi

Ichiro Omura

Takeshi Nakamura

Shinichi Suzuki

Kazunori Taguchi

Eisuke Suekawa

Kazuhiko Niwayama

Mikio Bessho

Kenji Oota

Yoshihiko Sunami

Hideki Haruguchi

Takeaki Asaeda

Shigeo Tooi

Youichi Ishimura

Junichiro Yamashita

Kenji Ohta

Yukitaka Hori

Tohru Iwahashi

Toshiro Hiramoto

Kenichi Honda

Norihisa Asano

Shinichi Ishizawa

Takuya Saraya

Kazuo Itou

Toshihiko Takakura

Munetoshi Fukui

Katsuyuki Ohshima

Kenichi Iwaguro

A semiconductor device includes an emitter layer of a first conductivity type, a collector layer of a first conductivity type, a drift layer of a second conductivity type provided between the emitter layer and the collector layer, an emitter electrode electrically connected to the emitter layer, a collector electrode electrically connected to the collector layer, one or a plurality of emitter-side gate electrodes arranged to face the emitter layer with an emitter-side gate insulating film interposed therebetween, a first high-concentration impurity layer of a second conductivity type provided between the emitter electrode and the emitter layer, the first high-concentration impurity layer having an impurity concentration higher than an impurity concentration of the emitter layer, an impurity layer of a first conductivity type provided between the drift layer and the collector electrode, one or a plurality of collector-side gate electrodes arranged to face the impurity layer with a collector-side gate insulating film interposed therebetween, and a second high-concentration impurity layer of a second conductivity type provided between the collector electrode and the impurity layer and having an impurity concentration higher than that of the impurity layer, in which a total length of a first facing region of the emitter-side gate electrode in a gate width direction, the first facing region facing the emitter layer with the emitter-side gate insulating film interposed therebetween, is longer than a total length of a second facing region of the collector-side gate electrode in a gate width direction, the second facing region facing the impurity layer with the collector-side gate insulating film interposed therebetween.

Semiconductor device

A semiconductor device includes a layer structure including a first gate electrode and a second gate electrode, and a first main electrode and a second main electrode that can be electrically connected through the layer structure. The threshold voltage of the second gate electrode is higher than the threshold voltage of the first gate electrode. In the α state and the β condition, the switching operation is performed using the first gate electrode, and in the γ state or the δ condition, the switching operation is performed using the second gate electrode.

Semiconductor device, power conversion apparatus, and method for driving semiconductor device

The semiconductor device includes: a transistor, and a body diode included in the transistor so that the body diode is anti-parallel to the transistor, and a diode anti-parallel connected to the bidirectional current-conduction device, wherein the bidirectional current-conduction device allows a first current and a second current to flow, and allows at least the second current to switch between conduction and non-conduction, the first current flowing in a first direction from a first main electrode of the transistor to a second main electrode facing the first main electrode, the second current flowing through the body diode in a second direction opposite to the first direction, and the diode is smaller in area than the bidirectional current-conduction device in a plan view.

The plurality of first control electrodes extend in a first direction in a planar view, the plurality of second control electrodes extend in a second direction in a planar view. A sum of lengths in the first direction of boundaries between the second semiconductor layer and the plurality of third semiconductor layers on a surface of the semiconductor substrate which faces the plurality of first control electrodes is set as a first gate total width. A sum of lengths in the second direction of boundaries between the fourth semiconductor layer and the plurality of fifth semiconductor layers on a surface of the semiconductor substrate which faces the plurality of second control electrodes is set as a second gate total width. A gate width ratio obtained by dividing the second gate total width by the first gate total width is equal to or higher than 1.0.

Each of a plurality of IGBT cells includes an n base layer formed in a semiconductor layer, a p base layer formed in a surface portion of the n base layer on a side of the first main surface, an n emitter layer formed in a surface portion of the p base layer, and a p collector layer formed in a surface portion of the semiconductor layer on a side of the second main surface. On a first main surface of the semiconductor layer, a gate electrode and an emitter electrode are formed. On a second main surface of the semiconductor layer, a collector electrode is formed. A pitch of the plurality of IGBT cells is 1/40 or more and 1/20 or less of a distance between the p base layer and the p collector layer.

A semiconductor device includes: a semiconductor base having a first main surface and a second main surface which are opposite to each other; a first main electrode formed on the first main surface and electrically connected to the semiconductor base; a first control electrode pad formed on the first main surface; a first insulating film interposed between the semiconductor base and the first control electrode pad; a peripheral withstand voltage holding structure formed in a peripheral region surrounding the first main electrode and the first control electrode pad on the first main surface; a second main electrode formed on the second main surface and electrically connected to the semiconductor base; a second control electrode pad formed on the second main surface; and a second insulating film interposed between the semiconductor base and the second control electrode pad, wherein the second control electrode pad is surrounded by the second main electrode.

Semiconductor device and inverter

A normally-off first gate channel region is provided on a first main surface side, in a region in a p base between an n base and an n emitter connected to an emitter electrode. On and off of the first gate channel region is controlled by a voltage of a first gate electrode. A normally-on second gate channel region is provided on a second main surface side, by an n-type region between an n collector electrically connected to a collector electrode and the n base. On and off of the second gate channel region is controlled by a voltage of a second gate electrode.

It is a purpose of the present invention to provide an insulated gate bipolar transistor device or the like that exhibits high performance and that is suitable for mass production. The insulated bipolar transistor device includes multiple trench structures including at least a trench gate, a first dummy trench, and a second dummy trench. The first dummy trench and the second dummy trench are configured as adjacent trenches. The trench gate is connected to a gate electrode layer. The first dummy trench and the second dummy trench are connected to an emitter electrode layer, and are not connected to the gate electrode layer. A first conductive source layer is also formed between the first dummy trench and the second dummy trench.

Insulated gate bipolar transistor device, manufacturing method for semiconductor device, and manufacturing method for insulated gate bipolar transistor device

Each of a P-side IGBT and an N-side IGBT connected in series to implement an arm includes a first gate and a second gate. In each of a drive circuit unit configured to control a voltage of the first gate with respect to a collector of the P-side IGBT, a drive circuit unit configured to control a voltage of the second gate with respect to an emitter of the P-side IGBT, and a drive circuit unit configured to control a voltage of the second gate with respect to a collector of the N-side IGBT, a signal processing circuit and an output circuit are electrically isolated from each other by an isolation structure.

A semiconductor chip and connection ends of corresponding external electrode terminals are encapsulated with a glass based sealing material, and the semiconductor chip includes a wide gap semiconductor element, and the electrodes of the semiconductor chip are connected to the end portions of the external electrode terminals by a silver based brazing member and/or pressure contact.

Semiconductor device having sealing structure for wide gap type semiconductor chip

A rotary printing press includes a plurality of printing units, including at least one multiple-printing unit having a plurality of printing devices arranged vertically in layers. A plurality of first web feed units each having a web roll support device are provided for the printing units in one-to-one correspondence. At least one second web feed unit having a web roll support device is provided as a counterpart to the first web feed unit corresponding to the multiple-printing unit. The printing press includes a web roll transport apparatus, which includes a web roll transport path provided in between the first web feed units and the second web feed unit and along the row of printing units, and a web roll transport device traveling along the web roll transport path.

Rotary printing press having printing units each having printing devices arranged vertically in layers

An object of the present invention is to improve the relationship between the switching loss and the conduction loss in a semiconductor device comprising a diode and a switching device made of silicon carbide, while suppressing occurrence of voltage oscillation of the device having a high amplitude. A resistor ( ) is connected in parallel to a diode ( ) made of silicon carbide. Although a resistive component of the diode ( ) varies widely with turn-on and turn-off of the diode ( ), connecting the resistor ( ) in parallel to the diode ( ) allows suppression of variations in a resistive component of an LCR circuit formed by the diode ( ) and an external wiring. Accordingly, the LCR circuit is unlikely to satisfy the condition of natural oscillation and an increase in the quality factor of the LCR circuit is suppressed.

Silicon carbide semiconductor switching device

A semiconductor device having a silicon carbide layer of a singular conductivity type. The silicon carbide layer includes a surface having a first region, a second region, and a third region sandwiched between the first region and the second region. An anode electrode having a Schottky contact with the first region, a cathode electrode having an ohmic contact with the second region, and a control electrode having a Schottky contact with the third region are included in the semiconductor device.

Semiconductor device having silicon carbide layer of predetermined conductivity type and module device having the same

A semiconductor device which can prevent an operation thereof from being uncontrollable to obtain a high reliability, and can be manufactured easily and can reduce a manufacturing cost. A p-type impurity layer containing a p-type impurity in a relatively high concentration is provided as an operation region of a diode in one of main surfaces of a silicon substrate containing an n-type impurity in a relatively low concentration and a plurality of ring-shaped Schottky metal layers are concentrically provided on the main surface of the silicon substrate around the p-type impurity layer with a space formed therebetween to surround the p-type impurity layer. A silicon oxide film is provided on the main surface of the silicon substrate around the p-type impurity layer and an anode electrode is provided on the p-type impurity layer.

Semiconductor device including at least one schottky metal layer surrounding PN junction

In order to reduce a turn-on time of a power switching semiconductor device at a low cost, a first main electrode divided into a plurality of segments forming segment rows of a multi-concentric circle and a control electrode surrounding the segments are formed on a front major surface of a semiconductor substrate, and a second electrode is formed on a rear major surface thereof, and a turn-on operation is performed between the first main electrode and the second main electrode with a control signal inputted from the control electrode, specifying a relationship between a width of a segment and a distance between adjacent segments, and others.

Growing community of inventors

Tokyo, Japan

Katsumi Satoh