Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Hitachi Computer Engineering Co., Ltd.

Vlsi Technology Research Association

Hatachi Ltd

Hitachi, Ind.

Katsumi Ogiue

Masanori Odaka

Akihisa Uchida

Satoru Isomura

Ikuro Masuda

Yukio Suzuki

Hideaki Uchida

Toshihiko Takakura

Yoichi Tamaki

Masato Iwabuchi

Daisuke Okada

Atsuo Watanabe

Takahide Ikeda

Masao Kawamura

Nobuo Tamba

Kazuhiro Akimoto

Atsushi Hiraishi

Osamu Saito

Keiichi Higeta

Akira Fukami

Mitsuru Hirao

Masayuki Ohayashi

Nobuhiko Ohno

Kouichirou Yamada

Tadashi Kuramoto

Kinya Mitsumoto

Masamori Kashiyama

Shuuichi Miyaoka

Akio Hayasaka

Hiroshi Murayama

Kazumichi Mitsusada

Hitoshi Abe

Masami Usami

Takeo Uchiyama

Toru Koizumi

Kazuo Itoh

Shinji Nakashima

Yoshikuni Kobayashi

Takeo Shiba

Noriyuki Sakuma

Yuji Yatsuda

Kanji Otsuka

Hiromichi Enami

Takahiro Onai

Kunihiko Yamaguchi

Kiichiro Mukai

Kazuo Nakazato

Kiyoji Ikeda

Yasushiro Nishioka

Hiroshi Shinriki

Masao Sekibata

Touji Mukai

Takahisa Nitta

Shinji Nakajima

Ichiro Mitamura

Toru Nakamura

Kaoru Ohgaya

Daisuke Okaka

Kunizou Sahara

Noriyoshi Okuda

Katsuya Mizue

Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.

Method of manufacturing a semiconductor integrated circuit device

In a gate array with a RAM which is disposed between first and second logic circuit blocks each of which having plural logic gates, by-pass signal lines which interconnect the logic circuit blocks are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines, such as word lines of the RAM, formed from a layer which is adjacent to the by-pass signal lines are disposed, with respect to a plan view layout arrangement of the main surface of a chip, so as to intersect the latter at right angles. In addition, interconnection pitches of signal lines in different wiring layers which extend parallel with each other are set so that noises are cancelled in differential sense circuits.

Semiconductor IC device having a RAM interposed between different logic

In order to provide high speed and low power consumption, a semiconductor integrated circuit is constructed to utilize both CMOS elements and bipolar transistors. The bipolar transistors are used in the output portions to take advantage of their speed of operation to allow rapid charging and discharging of output lines. In the meantime, the principal operating portions of the circuit use CMOS elements of low power consumption. This arrangement is particularly advantageous in memory circuits.

Semiconductor integrated circuit

Disclosed is a semiconductor integrated circuit wherein a logic circuit for exchanging signals with RAMS, with the RAMS being disposed centrally on the semiconductor chip or substrate, is divided into a plurality of logic circuits in accordance with the kind of signals and the divided logic circuits are disposed around the RAM in such a manner as to minimize the distance of signal transmission paths with the RAM and in order to attain high speed access to RAMS.

Semiconductor integrated circuit device with two variable delay lines in

Method of manufacturing semiconductor integrated circuit device

In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layer which extend parallel with each other are set so that noises are canceled in differential sense circuits.

Semiconductor integrated circuit device having a gate array with a ram

A logic circuit to be formed in a gate array is selected depending upon the value of the output load capacitance thereof, from among a CMOS circuit, a first Bi-CMOS circuit including an output bipolar transistor whose emitter size is set at a predetermined value, and a second Bi-CMOS circuit including an output bipolar transistor whose emitter size is larger than the emitter size of the output bipolar transistor of the first Bi-CMOS circuit. That is, the logic circuit is brought into a circuit form whose output load capacitance can be charged and discharged fastest. As a result, the logic circuit constructed in the gate array by adopting such a design technique has its operating speed raised. An improved structure is also provided for reducing wiring lengths by arranging bipolar transistors in adjacent basic cells to have mirror symmetry with one another. Further, particular gate width relationships are provided between MOSFETs within basic cells for reducing propagation delay and the required occupation area.

Semiconductor integrated circuit with bipolar transistors and MOSFETs

A semiconductor integrated circuit device having a structure in which each of the following regions, that is, a first region for forming the base and emitter regions of each of the bipolar transistors, a second region for forming the collector lead-out region of the bipolar transistor, and a third region for forming each of the MISFETs, is projected from the main surface of a semiconductor substrate, whereby it is possible to effect isolation between the MISFETs and between these MISFETs and the bipolar transistors with the same isolation structure and in the same manufacturing step as those for the isolation between the bipolar transistors. In this device, furthermore, the base region of the bipolar transistor is electrically and self-alignedly connected to a base electrode which is formed over the main surface so as to surround the emitter region. The bipolar transistor is characterized as a self-alignment transistor and that the insulating side wall spacers corresponding to the gate and base (emitter) electrodes are formed by a same lever.

Semiconductor integrated circuit device forming on a common substrate

A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body. The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.

Method of manufacturing semiconductor device with constant width deep

A bipolar SRAM which includes a forward bipolar transistor and a reverse bipolar transistor on an identical semiconductor substrate, is disclosed. Concretely, the base region of the reverse bipolar transistor is formed at a deeper position of the substrate than the base region of the forward bipolar transistor, thereby to heighten the cutoff frequency f.sub.T of the reverse bipolar transistor.

Semiconductor integrated circuit device having bipolar memory, and

This invention relates to a semiconductor integrated circuit device including highly self-aligned bipolar transistors. The semiconductor integrated circuit device a semiconductor body at least a first protruding portion and a hollow portion, disposed as a trench. The hollow portion being adjacent to the first protruding portion and being lower than an upper surface of the first protruding portion and including an isolation groove which is formed along a side surface of the protruding portion and in self-alignment with a peripheral edge portion of the upper surface of the first protruding portion. The device also has insulating material formed on a surface of the hollow portion so as to fill the insulation groove, a first semiconductor region of a first conductivity type formed in the first protruding portion, a portion of said first semiconductor region being exposed to the side surface of the protruding portion, a second semiconductor region of a second conductivity type opposite to the first conductivity type formed in the first protruding portion on the first semiconductor region, a third semiconductor region of the second conductivity type formed in the first protruding portion under the first semiconductor region and a polycrystalline silicon film formed on the insulating material in contact with at least the portion of the first semiconductor region exposed to the side surface of the protruding portion.

Semiconductor integrated circuit device with isolation grooves and

A semiconductor memory system includes a memory section formed on a semiconductor substrate and having decode means for decoding an address signal, and a logic section formed on the semiconductor substrate and having address signal forming means for forming an address signal for the memory section and address signal delivering means for delivering the address signal for the memory section to the decode means. The address signal delivered from the address signal delivering means is defined by complementary signals.

Semiconductor memory system for use in logic LSI's

In a gate array with a RAM, by-pass signal lines which interconnect a logic section and I/O unit circuit of the gate array are disposed so as to extend above the RAM. In order to minimize mutual interference, signal lines formed from a layer which is adjacent to the by-pass signal lines are disposed so as to intersect the latter at right angles. In addition, interconnection pitches in different layers which extend parallel with each other are set so that noises are cancelled in differential sense circuits.

Semiconductor integrated circuit device having a gate array with a RAM

Method of fabricating a semiconductor substrate, and semiconductor

Growing community of inventors

Hinode, Japan

Katsumi Ogiue