Fujitsu Corporation

Katsumi Homma

Toshiyuki Shibuya

Izumi Nitta

Hidetoshi Matsuoka

Makoto Mukai

Yoshirou Tanaka

A computer-readable, non-transitory medium stores a program that causes a computer to execute a process including acquiring a unique coefficient that is unique to a device in a circuit under test and is included in a function expressing fluctuation of leak current of the device; detecting as a group and based on the unique coefficient, devices having an identical or similar characteristic; converting first random variables into a single second random variable, the first random variables expressing fluctuation of leak current unique to each of the detected devices; yielding a function that expresses fluctuation of leak current of the detected devices, using the second random variable; and outputting the yielded function.

Analysis support computer product, apparatus, and method

A non-transitory, computer-readable recording medium stores therein a program causing a computer to execute calculating, using respective standard deviations of first delay distributions of delay variation independent to each element included in a path among parallel paths in a circuit, standard deviation of a first delay distribution of the path when modeled as a series circuit; correcting the standard deviation of the first delay distribution for each element, using the calculated standard deviation of the first delay distribution of the path and a standard deviation of a first delay distribution of the path obtained by a statistical delay analysis on the circuit; obtaining a correlation distribution representing a correlation between delay and leak current of the circuit by executing, using the corrected standard deviation of the first delay distribution for each element, correlation analysis between delay and leak current of the target circuit; and outputting the obtained correlation distribution.

Computer product, analysis support apparatus, and analysis support method

A computer-readable recording medium stores therein a program causing a computer that accesses a simulator to execute receiving a measured yield distribution that expresses an actually measured yield distribution concerning leak current of a circuit-under-design, and model data for leak current of a cell of the circuit-under-design; providing the simulator with the model data and values for a normal distribution concerning variation components of the leak current of the cell; acquiring the leak current of the circuit-under-design; calculating, based on the acquired leak current, an estimated yield distribution concerning the leak current of the circuit-under-design; calculating values for the normal distribution that minimize error between the measured yield distribution and the estimated yield distribution; setting an initial value to the normal distribution and the calculated values for the normal distribution to the normal distribution; and outputting the estimated yield distribution that is based on the leak current of the circuit-under-design.

Circuit design support computer product, apparatus, and method

A monitor position determining apparatus includes an acquiring unit that acquires design data concerning circuit elements arranged in a layout of a semiconductor device and for each of the circuit elements, yield sensitivity data indicative of a percentage of change with respect to a yield ratio of the semiconductor device; a selecting unit that selects, based on the yield sensitivity data, a circuit element from a circuit element group arranged in the layout; a determining unit that determines an arrangement position in the layout to be an installation position of a monitor that measures a physical amount in the semiconductor device in a measurement region, the arrangement position being of the circuit element that is specified from the design data acquired by the acquiring unit and selected by the selecting unit; and an output unit that outputs the installation position determined by the determining unit.

Monitor position determining apparatus and monitor position determining method

A leakage current analyzing apparatus receives input of data used for analysis and indicating intra/inter-chip variation concerning the gate length of transistors constituting cells in a circuit to be designed, where the inter-chip variation is handled as a discrete probability density distribution R. Using the data input, the leakage current analyzing apparatus obtains a cumulative probability density for a leakage current value (of the circuit) that is equal to or less than each arbitrary leakage current value Ito I. As a result, the leak rate of the circuit to be designed can be correctly obtained without limiting the shape of distribution.

Leakage current analyzing apparatus, leakage current analyzing method, and computer product

A delay analysis support apparatus that supports analysis of delay in a target circuit includes an acquiring unit that acquires error information concerning a cell-delay estimation error that is dependent on a characterizing tool; an error calculating unit that calculates, based on the error information and a first probability density distribution concerning the cell delay of each cell and obtained from the cell delay estimated by the characterizing tool, a second probability density distribution that concerns the cell-delay estimation error of each cell; and an linking unit that links the second probability density distribution and a cell library storing therein the first probability density distribution.

Delay analysis support apparatus, delay analysis support method and computer product

Fluctuations of cumulative delay value and delay dispersion in a path of a circuit are displayed graphically. Cumulative delay values of circuit elements in the path are obtained from delay analysis results of the circuit and dispersion is obtained from a probability density distribution of the delay of the circuit elements. Corresponding to the location of the circuit element in the path, the former and the latter are plotted on a coordinate plane.

Device and method for displaying delay analysis results, and computer product

A delay distribution of a partial path that passes through a node to which a plurality of signals is input and for which an estimation in a statistical MAX is predicted to be large, that is present on a critical path having large influence on a circuit delay, and that has high possibility of improving the circuit delay, among nodes in a circuit graph is calculated by the Monte Carlo simulation instead of the block based simulation, thereby increasing speed and accuracy of delay analysis.

Method and apparatus for supporting delay analysis, and computer product

Within-die delay distributions and die-to-die delay distributions of two arbitrary paths in an analysis target circuit are extracted from a delay distribution library, and an effect index indicative of a relative error of an overall path delay distribution of one path and an overall path delay distribution when the two paths are integrated as one path is calculated based on the within-die delay distributions and the die-to-die delay distributions of the two paths. When the effect index is determined to be equal to or above a threshold, the overall path delay distribution of the two paths integrated as one path is calculated. Hence, a path that affects an analysis result alone is selected to execute a statistical Max operation, thereby increasing a speed of delay analysis processing.

Delay analysis apparatus, delay analysis method and computer product

Delay analysis performed on a circuit having multiple parallel partial circuits (paths) involves recursively integrating two paths of the circuit using an all-element delay distribution that indicates delay based on performance of all circuit elements in a path and a correlation delay distribution that indicates delay based on correlation between circuit elements in the path. An all-element delay distribution is calculated for the integrated path using the all-element delay distributions of the two paths to be integrated. The all-element delay distributions and the correlation delay distributions of two paths to be integrated are used to calculate a total delay distribution for the integrated path. The total delay distribution is used with the all-element delay distribution for the integrated path to calculate a correlation delay distribution for the integrated path. Through recursive calculation, a delay distribution of the circuit is estimated.

Circuit delay analyzer, circuit delay analyzing method, and computer product

An apparatus includes: a detecting unit that detects a target path from among a plurality of paths in a target circuit based on a result of a delay analysis of the target circuit, wherein the result of the delay analysis includes delay data of a first circuit component of the target path; an extracting unit that extracts delay data of a second circuit component having an identical type to that of the first circuit component; and a generating unit that generates a directive for replacing the first circuit component with the second circuit component.

Method and apparatus for repeat execution of delay analysis in circuit design

A delay analyzing apparatus receives a result of timing analysis of a target circuit, and detects, from paths in the target circuit, critical paths based on the result of the timing analysis with a detecting unit. A first calculating unit calculates an average delay distribution of the paths other than the critical paths based on an average delay value of each of the critical paths. A second calculating unit calculates a probability density distribution of the critical paths, and a third calculating unit calculates a probability density distribution of all of the paths based on the average delay distribution. A fourth calculating unit calculates difference between a statistical delay value of the critical paths and a statistical delay value of all of the paths based on the probability density distribution of the critical paths and the probability density distribution of all of the paths.

Circuit delay analyzing method, circuit delay analyzing apparatus, and computer product

A delay analysis device includes a receiving unit that receives a result of a timing analysis of a target circuit to be analyzed, a detecting unit that detects critical paths having delays within a predetermined range, a statistical-delay computing unit that computes a statistical delay of the target circuit based on a cumulative probability distribution of the delays of the critical paths, and a probability-density-distribution computing unit that computes a probability density distribution of delay of a critical path that has the greatest delay in the result. The detecting unit detects x number of critical paths having cumulative delays within computed probability density distribution.

Delay analysis device, delay analysis method, and computer product

An input unit receives circuit information on a circuit. A first calculating unit calculates delay-distribution information of a data path and delay-distribution information of a clock path, based on the circuit information. A second calculating unit calculates delay-difference-distribution information between the data path and the clock path by using the delay-distribution information of the data path and the delay-distribution information of the clock path. A third calculating unit calculates a clock-delay value of the circuit based on the delay-difference-distribution information.

Method and apparatus for analyzing clock-delay, and computer product

When an electric current flowing through an electronic appliance is simulated by solving simultaneous linear equations defined depending on an analytic frequency, the simultaneous linear equations are solved in the direct method using a frequency other than the frequencies on both ends of an analytic frequency area as an analysis target, and the simultaneous linear equations are solved in the iterative method while transforming the simultaneous linear equations using the coefficient matrix analyzed in the direct method on the frequencies other than the above described frequency defined as the analysis target.

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Kawasaki, Japan

Katsumi Homma