Renesas Electronics Corporation

Mitsubishi Denki Kabushiki Kaisha

Matsushita Electric Industrial Co., Ltd.

Renesas Technology Corp.

Katsumi Eikyu

Atsushi Sakai

Tatsuya Kunikiyo

Hiroshi Yanagigawa

Akihiro Shimomura

Shigenobu Maeda

Takashi Ipposhi

Hiroyuki Umimoto

Kyoji Yamashita

Yotaro Goto

Kazuhisa Mori

Satoru Tokuda

Mutsumi Kobayashi

Katsuhiro Ohtani

Yoshito Nakazawa

Eiji Tsukuda

Yukio Nishida

Masao Sugiyama

Kenichiro Sonoda

Yoshikazu Nagamura

Masato Fujinaga

Yoshinori Kaya

Masami Sawada

Norihiko Kotani

Yoshihiro Nomura

Takeshi Kitani

Tomohiro Imai

Kiyoshi Ishikawa

Hiroyuki Arie

Ryuuji Umemoto

Fumihito Ota

Yuta Nabuchi

A semiconductor device includes a cell region in which a plurality of unit cells are formed, and an outer peripheral region surrounding the cell region in plan view. Each of the plurality of unit cells includes a semiconductor substrate having a drift region, a body region, a source region, a pair of first column regions, and a gate electrode formed in a trench with a gate insulating film interposed therebetween. A well region is formed on a surface of the drift region in the outer peripheral region. A second column region is formed in the drift region below the well region and extends in Y and X directions so as to surround the cell region. The well region is connected to the body region, and the second column region is connected to the well region.

Semiconductor device and method of manufacturing the same

A semiconductor device includes a semiconductor substrate, a first source region and a first drain region each formed from an upper surface of the semiconductor substrate, a first gate electrode formed on the semiconductor substrate between the first source region and the first drain region via a first gate dielectric film, a first trench formed in the upper surface of the semiconductor substrate between the first gate dielectric film and the first drain region in a gate length direction, a second trench formed in the upper surface of the semiconductor substrate between the gate dielectric film and the first drain region in the gate length direction, the second trench being shallower than the first trench, and a first dielectric film embedded in the first trench and the second trench. The first trench and the second trench are in contact with each other in a gate width direction.

Semiconductor device

To reduce on-resistance while suppressing a characteristic variation increase of a vertical MOSFET with a Super Junction structure, the vertical MOSFET includes a semiconductor substrate having an n-type drift region, a p-type base region formed on the surface of the n-type drift region, a plurality of p-type column regions disposed in the n-type drift region at a lower portion of the p-type base region by a predetermined interval, a plurality of trenches whose bottom surface reaches a position deeper than the p-type base region and that is disposed between the adjacent p-type column regions, a plurality of gate electrodes formed in the plurality of trenches, and an n-type source region formed on the side of the gate electrode in the p-type base region.

An IGBT capable of handling high-speed switching while reducing a leakage current of a semiconductor device including the IGBT is provided. The semiconductor device according to one embodiment includes an IGBT including a p-type collector layer on a back surface of a silicon substrate and a dislocation suppressing layer for forming a hetero junction with silicon in the p-type collector layer. The dislocation suppressing layer includes a silicon germanium (SiGe) layer.

A semiconductor device includes a semiconductor substrate, a first dielectric film, a conductive film, at least one ferroelectric film, a second dielectric film, a memory gate electrode, a third dielectric film and a control gate electrode. The semiconductor substrate includes a source region and a drain region. The semiconductor substrate includes a first region and a second region between the source region and the drain region. The first dielectric film is formed on the first region. The conductive film is formed on the first dielectric film. The at least one ferroelectric film is formed on one hart of the conductive film. The second dielectric film is formed on the other part of the conductive film. The memory gate electrode is formed on the ferroelectric film. The third dielectric film is formed on the second region. The control gate electrode is formed on the third dielectric film.

In a trench gate type power MOSFET having a super-junction structure, both improvement of a breakdown voltage of a device and reduction of on-resistance are achieved. The trench gate and a column region are arranged so as to be substantially orthogonal to each other in a plan view, and a base region (channel forming region) and the column region are arranged separately in a cross-sectional view.

A gate electrode is formed on a semiconductor substrate between an n-type source region and an n-type drain region via a first insulating film. The first insulating film has second and third insulating films adjacent to each other in a plan view and, in a gate length direction of the gate electrode, the second insulating film is located on an n-type source region side, and the third insulating film is located on an n-type drain region side. The second insulating film is thinner than the third insulating film. The third insulating film is made of a laminated film having a first insulating film on the semiconductor substrate, a second insulating film on the first insulating film, and a third insulating film on the second insulating film, and each bandgap of the three insulating films is larger than that of the second insulating film.

A semiconductor device according to an embodiment comprises: a cell portion in which a vertical type MOSFET is formed; and a termination portion arranged adjacent to the cell portion. The termination portion includes a connection trench gate provided along a first direction. The cell portion includes: a plurality of first column regions provided along a second direction intersecting the first direction; and a plurality of trench gates provided along the second direction such that two trench gates are arranged between the two adjacent first column regions. The plurality of trench gates extend from the cell portion to the termination portion and are connected to the connection trench gate. The plurality of first column regions extend from the cell portion to the termination portion, and the termination portion includes a plurality of second column regions different from the plurality of first column regions.

The semiconductor device SDincludes a first wiring Mand a second wiring M The semiconductor device includes a first conductor pattern DM, a first via Vin contact with the first wiring Mand the second wiring M, and a second via DV,DV,DV,DVin contact with the first conductor pattern DM and the second wiring M In plan view, the distance between the second via DVclosest to the corner portion CI of the second wire Mand the corner portion CI is shorter than the distance between the first via Vand the corner portion CI, and the distance between the second vias adjacent to each other is shorter than the distance between the second via DVclosest to the first via Vand the first via V

The semiconductor device has a wiring M, an interlayer insulating film ILformed on the wiring M, and two wirings Mformed on the interlayer insulating film IL, and the wiring Mis connected to the wiring Mby a conductor layer PGformed in the interlayer insulating film IL. A recess CCis formed on the upper surface ILof the interlayer insulating film IL, and the recess CCis defined by a side surface Sconnected to the upper surface ILand a side surface Sconnected to the side surface S, and the side surface Sis inclined so that the width WCof the recess CCdecreases in the direction from the upper surface ILof the interlayer insulating film ILtoward the upper surface ILof the interlayer insulating film IL

Semiconductor device having a multilayer structure

In an LDMOS having an element isolation region of an STI structure, there is prevented an occurrence of insulation breakdown which might be caused when electrons generated in a semiconductor substrate near an edge portion of a bottom face of the element isolation region are poured into a gate electrode. Immediately over an upper surface of an offset region adjacent to the element isolation region embedded in a main surface of the semiconductor substrate between a source region and a drain region, there is provided a trench penetrating a silicon film forming the gate electrode. As a consequence, the silicon film and a metal film for filling the trench form the gate electrode.

To provide an imaging device equipped with a photodiode, which is capable of enhancing both of a capacity and sensitivity. In an area of a P-type well in which a photodiode is formed, a P-type impurity region is formed from the surface of the P-type well to a predetermined depth. Further, an N-type impurity region is formed to extend to a deeper position. N-type impurity regions and P-type impurity regions respectively extending in a gate width direction from a lower part of the N-type impurity region to a deeper position so as to contact the N-type impurity region are alternately arranged in a plural form along a gate length direction in a form to contact each other.

Imaging device

To provide a semiconductor device having a photoelectric conversion element having a high sensitivity, causing less blooming, and capable of providing a highly reliable image. The semiconductor device has a semiconductor substrate, a first p type epitaxial layer, a second p type epitaxial layer, and a first photoelectric conversion element. The first p type epitaxial layer is formed over the main surface of the semiconductor substrate. The second p type epitaxial layer is formed so as to cover the upper surface of the first p type epitaxial layer. The first photoelectric conversion element is formed in the second p type epitaxial layer. The first and second p type epitaxial layers are each made of silicon and the first p type epitaxial layer has a p type impurity concentration higher than that of the second p type epitaxial layer.

Semiconductor device and method of manufacturing same

A plurality of word lines (WL) are provided in parallel to one another and a plurality of bit lines (BL) are provided in parallel to one another, intersecting the word lines (WL) thereabove. MRAM cells (MC) are formed at intersections of the word lines and the bit lines therebetween. MRAM cells (MC) are provided so that an easy axis indicated by the arrow has an angle of 45 degrees with respect to the bit lines and the word lines. Thus, an MRAM capable of cutting the power consumption in writing is achieved and further an MRAM capable of reducing the time required for erasing and writing operations is achieved.

Magnetic memory device capable of passing bidirectional currents through the bit lines

A CBCM measurement device includes a PMIS transistor, an NMIS transistor, a first reference conductor section connected to a first node, a second reference conductor section, with a dummy capacitor being formed between the first and second reference conductor sections, a first test conductor section connected to a second node, and a second test conductor section, with a test capacitor being formed between the first and second test conductor sections. The transistors are turned ON/OFF by using control voltages Vand V, and the capacitance of a target capacitor in the test capacitor is measured based on currents flowing through the first and second nodes. The capacitance measurement precision is improved by, for example, increasing a dummy capacitance.

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Tokyo, Japan

Katsumi Eikyu