Kabushiki Kaisha Toshiba

Toshiba Microelectronics Corporation

Katsumasa Hayashi

Toshiyuki Kondo

Yutaka Ishibashi

Masahisa Sonoda

Tomoya Osaki

Seishi Irie

According to one embodiment, a semiconductor memory device includes a substrate, an upper-layer wire provided on the substrate, a lower-layer wire provided on the substrate, a memory cell located at an intersection of the upper-layer wire and the lower-layer wire and includes a diode and a storage layer, a conductive layer located between the upper-layer wire and the memory cell in a direction perpendicular to the substrate surface, and an interlayer insulating film provided between memory cells. The position of an interface between the upper-layer wire and the interlayer insulating film is lower than a top surface of the conductive layer.

Method of manufacturing a semiconductor memory device

Diode and storage layer semiconductor memory device

A semiconductor device includes a semiconductor substrate, first and second CMOS inverter circuits formed on the semiconductor substrate and constituting an SRAM memory cell, each inverter circuit having input and output terminals, and first and second resistance elements formed in the semiconductor substrate and having respective one ends connected to a gate electrode pattern serving as input terminals of the first and second CMOS inverter circuits and the respective other ends connected to electrodes serving as output terminals of the first and second CMOS inverter circuits. The gate electrode pattern includes an underside on which a gate insulation film is formed, the gate insulation film being located between the semiconductor substrate and the gate electrode pattern and having an opening. The first and second resistance elements include respective portions adjacent to the gate electrode pattern, at which portions the first and second resistance elements are electrically connected via the opening to the gate electrode pattern located over the opening.

Semiconductor device and method of fabricating the same

A semiconductor memory device includes a cell array having matrix-like arrayed plural SRAMs on a semiconductor substrate having an N-well and P-well. The N-well and the P-well are isolated from each other with an isolation region each having a shallow trench structure. Each memory cell includes two CMOS inverter circuits having input and output nodes making a cross-coupled connection. First and second capacitors are connected between each gate node of two CMOS inverter circuits and the N-well and/or N-well.

Semiconductor memory device having a shallow trench isolation structure

Growing community of inventors

Yokkaichi, Japan

Katsumasa Hayashi