Sharp Kabushiki Kaisha Corporation

Nanosys, Inc.

Sharp Laboratories of America, Inc

Sharp Microelectronics Technology, Inc.

Katsumasa Fujii

Sheng Teng Hsu

Hidechika Kawazoe

Hiroshi Iwata

Akihide Shibata

Eiji Aoki

J Wallace Parce

Paul John Schuele

David P Stumbo

Xiangfeng Duan

Hiroshi Ohki

Francisco A Leon

Jeffrey L Miller

Jong Jan Lee

James M Hamilton

Tetsu Negishi

Samuel Edward Martin

Cheri X Y Pereira

Yasunobu Okada

Yutaka Takafuji

Yasuo Torimaru

Tsutomu Ashida

Tomoya Baba

Kiyotoshi Nakagawa

Akiyoshi Mutou

The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.

Methods for nanowire alignment and deposition

An integrated circuit device of the present invention includes a substrate on which at least two types of nano wire element are provided. These nano wire elements have functions and materials different from each other. The nano wire elements are constituted by nano wires having sizes differing depending on types of nano wire element. With this, it is possible to dramatically improve a function of the integrated circuit device, as compared with an integrated circuit device including a substrate on which one type of nano wire element is provided.

Integrated circuit device, manufacturing method thereof, and display device

A semiconductor device comprises: a semiconductor substrate on which a silicon germanium film, a carbon-containing silicon film and a silicon film are formed in this order and a gate electrode on the semiconductor substrate with intervention of a gate oxide film, wherein a channel region of the semiconductor device the is formed in the carbon-containing silicon film or wherein a channel region of the semiconductor device is formed in the silicon germanium film.

Semiconductor device with NMOS including Si:C channel region and/or PMOS including SiGe channel region

An electrostatic discharge protection device is provided at an input or output of a semiconductor integrated circuit for protecting an internal circuit from an electrostatic surge flowing into or out of the integrated circuit. The electrostatic discharge protection device may include a thyristor, and a trigger diode for triggering the thyristor (e.g., with a low voltage). The trigger diode may include an n-type cathode high impurity concentration region; a p-type anode high impurity concentration region; and an insulator section for electrically insulating a silicide layer formed on a surface of the cathode region from another silicide layer formed on a surface of the anode region.

Electrostatic discharge protection device for semiconductor integrated circuit, method for producing the same, and electrostatic discharge protection circuit using the same

An electrostatic discharge protection device according to the present invention is provided at an input or an output of a semiconductor integrated circuit for protecting an internal circuit of the semiconductor integrated circuit from an electrostatic surge flowing into or out of the semiconductor integrated circuit. The electrostatic discharge protection device includes: a thyristor; and a trigger diode for triggering the thyristor with a low voltage. The trigger diode includes: an n-type cathode high impurity concentration region; a p-type anode high impurity concentration region; and an insulator section for electrically insulating a silicide layer formed on a surface of the n-type cathode high impurity concentration region from another silicide layer formed on a surface of the p-type anode high impurity concentration region.

Electrostatic discharge protection device for semiconductor integrated circuit method for producing the same and electrostatic discharge protection circuit using the same

A MOS transistor having a multilevel gate oxide layer is provided for use in an ESD protection circuit. A thick gate oxide layer near the drain insures that the transistor has a relatively large drain to gate breakdown voltage. A thin gate oxide layer near the source permits the gate voltage to turn the transistor on and off with rapid switching speeds. The thick portion of the MOS transistor multilevel gate oxide layer is formed with a local oxidation of silicon (LOCOS) process, while the thin gate layer is formed in a separate step. An ESD protection circuit and method for fabricating the above-mentioned multilevel gate oxide layer MOS transistor are also provided.

Method for fabricating a LOCOS MOS device for ESD protection

Locos MOS device for ESD protection

A metal oxide semiconductor device is featured by the provision of a covering element for covering a channel region of the semiconductor device there being interposed therebetween an insulating layer. The covering element is connected to at least one electrode selected from the drain electrode, the source electrode and the gate electrode. Therefore, the electrical level of the covering element is fixed.

High voltage MOS transistor

Growing community of inventors

Yamatokoriyama, Japan

Katsumasa Fujii