Kabushiki Kaisha Toshiba

Katsujiro Tanzawa

Akio Nakagawa

Tsuneo Ogura

Hajime Nagano

Yukihiro Ushiku

Kazuyoshi Furukawa

Norihiko Tsuchiya

Shinichi Nitta

Junji Sugamoto

Katsuya Okumura

Tsutomu Sato

Ichiro Mizushima

Takashi Yamada

Hiroaki Yamada

Soichi Nadahara

Masao Iwase

Hiroshi Matsushita

Tsunetoshi Arikado

Moriya Miyashita

Yuso Udo

Yoshihiro Yamaguchi

Kiminori Watanabe

Kiyoshi Fukuda

Kazuyoshi Furukama

A semiconductor wafer has a bevel contour formed along the periphery thereof, products formed on the wafer, and an ID mark formed on the bevel contour. The ID mark shows at least the properties, manufacturing conditions, and test results of the products.

Semiconductor wafer with ID mark, equipment for and method of manufacturing semiconductor device from them

A method of inspecting a semiconductor wafer, comprises removing a device structure film on the semiconductor wafer with a chemical solution to expose a crystal surface of the semiconductor wafer; coating a protected area, which is a part of the crystal surface of the semiconductor wafer, with a mask material for protecting the crystal surface of the semiconductor wafer; etching the semiconductor wafer selectively, thereby making a crystal defect in a non-protected area, which is a part of the crystal surface of the semiconductor wafer that is not coated with the mask material, appear after the crystal surface is coated with the mask material; removing the mask material after the selective etching; carrying out quantitative measurement of the protected area and the non-protected area using an optical defect inspection apparatus or a beam-type defect inspection apparatus; and calculating the number of crystal defects of the semiconductor wafer base on the result of the measurement.

Method of inspecting semiconductor wafer

A support-side substrate having a thermal oxide film on the major surface is bonded to an active-layer-side substrate having a thermal oxide film on the major surface while making the major surfaces oppose each other. The active-layer-side substrate and part of the oxide film are selectively etched from a surface opposite to the major surface of the active-layer-side substrate to a halfway depth of the buried oxide film formed from the thermal oxide films at the bonding portion. A sidewall insulating film is formed on the etching side surface portion of the active-layer-side substrate. Then, the remaining buried oxide film except that immediately under the active-layer-side substrate is selectively etched. A single-crystal semiconductor layer is formed on the support-side substrate exposed by removing the buried oxide film.

Element formation substrate, method of manufacturing the same, and semiconductor device

A treatment method of a semiconductor wafer includes treating the semiconductor wafer in a first solution having at least one kind of an oxidative acid and an oxidizing agent and treating the semiconductor wafer in a second solution having at least one of HF and NHF.

Semiconductor wafer treatment method, semiconductor wafer inspection method, semiconductor device development method and semiconductor wafer treatment apparatus

Element formation substrate for forming semiconductor device

A dielectric isolation substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semiconductor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer, and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectric isolation substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.

Process of making a semiconductor device using a silicon-on-insulator

Dielectrically isolated high and low voltage substrate regions

A dielectrically isolated substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semicondcutor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer, and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectrically isolated substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.

Dielectrically isolated substrate with isolated high and low breakdown

A dielectrically isolated substrate comprises a first semiconductor wafer, a second semiconductor wafer bonded on the first semiconductor wafer with a first insulating layer interposed therebetween, a semiconductor layer formed on the second semiconductor wafer, a first groove formed in the semiconductor layer and the second semiconductor wafer so as to reach the first insulating layer, thereby isolating the semiconductor layer and the second semiconductor wafer and a second insulating layer formed on the side face of the first groove or embedded in the first groove. In this dielectrically isolated substrate, a high breakdown voltage element and a low breakdown voltage element are formed in a region isolated by the first groove.

Dielectrically isolated substrate and semiconductor device using the same

A dielectrically isolated semiconductor wafer substrate includes first and second semiconductive layers bonded to each other by a direct bonding technique in such a manner that an insulative layer is sandwiched therebetween. The first semiconductive layer is a first silicon layer having a (100) or (110) crystal surface orientation, while the second semiconductive layer is a second silicon layer having a (111) crystal surface orientation. Thereafter, a peripheral portion of the resultant substrate is removed, and a substrate of a slightly smaller size is obtained which is provided with an additionally formed new orientation flat.

Dielectrically isolated semiconductor substrate

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Yokohama, Japan

Katsujiro Tanzawa