Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Socionext Inc.

Katsuji Satomi

Masayoshi Kinoshita

Jun Kajiwara

Hironori Akamatsu

Shiro Sakiyama

Katsuhiro Ootani

Akira Yamamoto

Shinichi Yamamoto

Hiroyuki Nakahira

Kazuo Itoh

Marefusa Kurumada

Shirou Sakiyama

Hirohisa Ohtsuki

Hiroyuki Yamauchi

Makoto Kojima

Yoshinobu Yamagami

Satoshi Ishikura

Shoichi Yoshizaki

Toshio Terano

Tomohiro Kurozumi

Hiroo Yamamoto

Kazuhiro Takemura

A memory cell power supply circuit for each column includes a first PMOS transistor and a second PMOS transistor connected together in series between a first power supply and a second power supply. A connection point between the first and second PMOS transistors is output as a memory cell power supply. A control signal which is based on a column select signal and a write control signal is input to a gate terminal of the first PMOS transistor. A signal which is an inverted version of the signal input to the gate terminal of the first PMOS transistor is input to a gate terminal of the second PMOS transistor.

Semiconductor storage device

A control circuit supplies a word line drive voltage to one of m word lines which corresponds to a memory cell to which data is to be written, during a word line drive period including a first period and a second period following the first period, to decrease current capabilities of first and second load transistors included in the memory cell during the first period, and increase the current capabilities of the first and second load transistors during the second period.

Semiconductor memory device

In a semiconductor memory device, a non-volatile element sectionstores information necessary for rescuing a main memory cell, as storage information, in a non-volatile element. When rescue information Sis newly outputted by a redundancy rescue section, a rescue determination sectiondetermines whether or not a main memory cell is to be rescued, based on storage information Sstored in the non-volatile element section, and the rescue information Swhich is newly outputted. The non-volatile element sectionrenews the storage information based on a determination result from the rescue determination section. Thus, on the assumption that power is turned off each time a voltage condition is changed, the semiconductor memory deviceis capable of determining whether or not the rescue is to be performed, based on results of testings performed under a plurality of voltage conditions.

A semiconductor memory device is provided which can reliably detect a memory cell which has an unstable operation due to a small memory cell current. A bit line drive circuit is provided with respect to each pair of first and second bit lines, and has a configuration which can decrease a potential of a selected one of the pair of first and second bit lines. During a test operation, the first bit line in conduction with an H-side memory holding node of a memory cell is grounded for a predetermined time, thereby reducing a potential difference between the pair of first and second bit lines.

Semiconductor memory device having read operation testing function

In data read, a single read global bit line is shared with a plurality of local bit lines.

Semiconductor memory device realizing high-speed access

A static random access memory (SRAM) includes a memory array, a sense amplifier circuit, a replica circuit and a dummy cell. The replica circuit has the same elements as memory cells, and includes plural replica cells which output a signal whose level corresponds to the number of stages provided to a common replica bit line. The dummy cell is connected as a load with the common replica bit line. The source of a drive transistor of the dummy cell is connected with a power source which is at the High level. This suppresses a leak current flowing from a replica bit line to the dummy cell.

Static random access memory (SRAM) with replica cells and a dummy cell

Over a memory cell array region of a static RAM (random access memory), dummy wire patterns are formed such that each dummy wire pattern covers 2&#xd7;2 horizontally and vertically-adjacent intersection points of word lines and bit lines, and horizontally-running wire channels and vertically-running wire channels are formed between the dummy wire patterns in a lattice configuration. Then, a signal line is automatically arranged to extend through any of the wire channels. The dummy wire patterns are provided in a layer lying on the word lines, and the signal line is provided as a metal line extending in the same layer as that of the dummy wire patterns.

Semiconductor device having a layout configuration for minimizing crosstalk

A dummy cell includes two series-connected OFF-state transistors, one end of the series circuit which is formed by these two transistors is connected with a constant voltage source, and the other end of the series circuit is connected with a replica bit line. This suppresses a leak current flowing from the replica bit line to the dummy cell and therefore gives optimal start-up timing to a sense amplifier circuit.

Semiconductor memory device and circuit layout of dummy cell

A semiconductor memory device may include: (1) a word line drive circuit, having a drive transistor disposed between a positive power supply and a word line, (2) a circuit for turning the drive transistor OFF after an output of the word line drive circuit reaches a high level, and (3) a word-line-voltage increasing circuit for increasing a voltage of the word line after the drive transistor turns OFF. The word-line-voltage increasing circuit includes a coupling capacitor, one end of which is connected to the word line, and a capacitor drive circuit, an output end of which is connected to the other end of the coupling capacitor. The capacitor drive circuit switches its output from a low level to a high level at a timing when the drive transistor is OFF.

Positive/negative bit lines are arranged on a second-layer interconnection the VDD power supply interconnection is arranged between the positive/negative bit lines, the word line is arranged on a third-layer interconnection, and the VSS power supply interconnection is arranged on a fourth-layer interconnection. Alternatively, the word line is arranged on the second-layer interconnection, the positive/negative bit lines are arranged on the third-layer interconnection, the VDD power supply interconnection is arranged between the positive/negative bit lines, and the VSS power supply interconnection is arranged on the fourth-layer interconnection. Alternatively, the VDD power supply interconnection is arranged on the second-layer interconnection, the positive/negative bit lines are arranged on the third-layer interconnection, the word line is arranged on the fourth-layer interconnection, and the VSS power supply interconnection is arranged on the fifth-layer interconnection.

A semiconductor memory device has a SRAM memory cell comprising: a first inverter including a first nMOS transistor and a first pMOS transistor; a second inverter including a second nMOS transistor and a second pMOS transistor; a third nMOS transistor; and a fourth nMOS transistor, wherein a first diffusion region forming the first and third nMOS transistors and a second diffusion region forming the second and fourth nMOS transistors, respectively, are arranged in linear shapes without having any bent part, and driving capabilities of the first and second nMOS transistors are higher than those of the third and fourth nMOS transistors.

Semiconductor SRAM having linear diffusion regions

N-channel MOS transistors are connected to bit lines so as to correspond to the data to be read out. A constant current outputting circuit uses an off leakage current of load transistors similar to the N-channel MOS transistors as a reference current to constitute a current mirror circuit having a mirror ratio according to the number of the N-channel MOS transistors connected to each bit line. P-channel MOS transistors of the constant current outputting circuit are connected to the bit lines and supply a current according to the off leakage currents of the N-channel MOS transistors. Thus, malfunctions caused by such as off leakage currents of transistors or the like can be reliably prevented without causing an increase in access time.

Read only memory

A power supply circuit according to the present invention is a power supply circuit formed on a semiconductor chip, including: an output transistor section outputting a power supply voltage; and a control circuit for controlling the output transistor section. The output transistor section is arranged in the vicinity of an external input/output terminal of the semiconductor chip.

Method for designing power supply circuit and semiconductor chip

Method of designing power supply circuit and semiconductor chip

In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors through having different on-resistances, which are operated nadescending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor

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Osaka, Japan

Katsuji Satomi