Fujitsu Corporation

Katsuji Hirochi

Takahiro Kato

Yoshiki Shimauchi

Takanori Sugihara

A Schmitt circuit for a semiconductor integrated circuit has resistances of predetermined resistors of the Schmitt circuit respectively selected from a plurality of resistances so as to obtain desired threshold voltages by selecting electrodes to which wiring is connected when producing the semiconductor integrated circuit according to the master slice method. Thus the Schmitt circuits have different threshold voltages depending on the selection of the electrodes to which the wiring is connected.

Schmitt circuit for semiconductor integrated circuit

A transistor-transistor logic circuit, i.e., TTL circuit includes at least one input terminal (IN; IN.sub.1, IN.sub.2), an output transistor (T10, T1), and elements (1, 2, T11, T12; 3, 4, T2) operatively connected between an input terminal and the base of an output transistor. The elements include a plurality of delay parts, each having a different signal propagation delay time respectively which feed base currents to the base of the output transistor in and at a different times. As a result, a quick change in the output is prevented and thus an overshoot, ringing or noise can be prevented, while realizing an increased driving ability. At the same time, optimum output characteristics can be obtained according to a load to be driven by the TTL circuit.

Transistor-transistor logic circuit

A gate array LSI device having inner gate circuits whose performance is not affected by the load condition and having a large fan-out number. The inner gate circuit comprises one or more PNP-type transistors, each of which receives an input signal at the base thereof, a first NPN-type transistor whose base is connected to the emitters of the PNP-type transistors, and an output buffer circuit. The output buffer circuit includes a second NPN-type transistor, which is controlled by the signal at the emitter of the first NPN-type transistor and outputs electric charges from an output terminal, and a third NPN-type transistor, which is controlled by the signal at the collector of the first NPN-type transistor and which is connected in series with the second NPN-type transistor so as to supply a charging current to the output terminal.

Growing community of inventors

Kawasaki, Japan

Katsuji Hirochi