Hitachi, Ltd.

Renesas Technology Corp.

Katsuichi Tomobe

Takeshi Miyazaki

Takashi Hotta

Teppei Hirotsu

Kotaro Shimamura

Yoshitaka Takahashi

Tetsuya Fukuoka

There is provided a semiconductor integrated circuit which assures sufficiently lower power consumption of a translation look-aside buffer without deterioration of operation rate performance thereof. In the translation look-aside buffer to convert logical address into physical address, a clock enable generating circuit is provided to stop the operation clock to be supplied to the tag memory and entry memory of the translation look-aside buffer while the virtual memory valid bit Vs of the status register indicating access to the virtual memory is '0', or while the cache-stall signal is outputted because of miss-hit in the cache, or when the access is issued with the same logical page address to the area other than the boundary area of the address range.

Semiconductor integrated circuit

A semiconductor integrated circuit to be connected to a PCI bus, having a configuration register. The size of an address space mapped to the semiconductor integrated circuit depends on the size of readable and writable region (Fv) of a base address register () that the configuration register has. The size of the readable and writable region of the base address register can be changed by a mask circuit (). The size of a local address space can be set to be variable according to the number of mask bits specified by a mask signal. For example, also in the case where a plurality of PCI devices are used, a memory space mapped to each device can be selectively reduced in size and as such, it is also possible to cope with the case where finite resources are mapped to many PCI devices to construct a system.

In an information processing apparatus, a user having no knowledge of a designer of an LSI modifies a floorplan of the LSI without deteriorating the performance of the LSI. The designer who designs the LSI uses a circuit designing apparatus to store circuit information including a functions of each of blocks constituting the LSI, a floorplan regarding allocation of the blocks, and evaluation indices which are the know-how of the designer, with being associated with each other. The user uses a floorplan modifying apparatus to modify the floorplan and to evaluate the modified floorplan according to the evaluation indices.

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Ome, Japan

Katsuichi Tomobe