Fujitsu Corporation

Katsuhisa Kubota

Kenji Nakamura

Kazuharu Nakano

Kunitoshi Yamamoto

A clock signal adjusting method and apparatus are applicable to an information processing system in which clock signals are distributed from a clock generating unit to a plurality of load units, each of the plurality of load units having at least a load element operated in synchronism with a clock signal input to each of the load units. In the clock signal adjusting method and apparatus, delay times set in each of a plurality of delay units are measured in accordance with setting instructions, each of the plurality of delay units delaying an input signal by a delay time set therein, setting instructions corresponding to delay times to be set in the plurality of delay units are input to the plurality of delay units based on measuring results obtained in the previous step, reference phase signals having predetermined phase differences are generated based on outputs of the plurality of delay units, and a phase of the clock signal distributed for the load element in each of the load units is adjusted based on phases of the reference phase signals thus generated.

Clock signal adjusting method and apparatus

A flip-flop circuit has a master circuit including a static flip-flop with a feedback loop, and a slave circuit including a dynamic flip-flop. In the flip-flop circuit, a clock signal is applied to the master circuit and the slave circuit. A clock width of the clock signal is determined by a time period from a clock edge for taking data into the master circuit to another clock edge for closing the master circuit, and is set to less than a given time period.

Flip-flop circuit and electronic device including the flip-flop circuit

A clock adjustment system for economically adjusting the output phases of a printed circuit board and an IC comprises a gate circuit for connecting an input of a measured circuit to an output. By turning the gate circuit on and by observing the oscillation of a measured circuit, the phase of the measured circuit is adjusted.

Apparatus for measuring clock pulse delay in one or more circuits

An ECL latch circuit comprises a data input part and a latch part. The data input part includes input transistors coupled in parallel and having bases for respectively receiving an input data and a clock signal, and an output transistor applied with a reference voltage. The data input part samples the input data responsive to the clock signal and outputs a level shifted data signal from a collector of the output transistor. The latch part includes a transistor which has a base for receiving the same clock signal, an emitter coupled transistor pair having bases respectively applied with the reference signal and an output signal of the ECL latch circuit, and a transistor having a base coupled to the collector of the output transistor and an emitter coupled to the base of the latter of the transistor pair.

Emitter coupled logic latch circuit

A test system for a random access memory includes a clock pulse width varying unit for varying a pulse width of driving pulses for a random access memory. A first latch is connected to an address input circuit of the random access memory for receiving the output clock signal of the clock pulse width varying unit and latching an address input signal at the leading edge of the output clock signal. A second latch is connected to a data output circuit of the random access memory for latching a data output signal. Both the first and second latches are supplied with the same clock signals from the clock pulse width changing unit, and a comparison unit is connected to a data output circuit of the random access memory for comparing the output of the random access memory with a predetermined expectation value. The output of the comparison unit is latched by the trailing edge of the clock pulse in the second latch.

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Kawasaki, Japan

Katsuhisa Kubota