Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Katsuhiro Uchimura

Yasuko Yoshida

Kota Funayama

Michimoto Kaminaga

Shuji Matsuo

Yutaka Takeshima

Masashi Sahara

Masanori Kojima

Fumiaki Endo

Kazuya Horie

Kazuhiro Toi

Masakazu Nakano

Hideaki Kanazawa

Masakazu Sugiura

In a memory cell forming region including a dummy cell region, a plurality of fins which are parts of a semiconductor substrate, protrude from an upper surface of an element isolation portion and are formed adjacent to each other. A distance between a fin closest to a dummy fin among the plurality of fins and the dummy fin is shorter than a distance between two fins adjacent to each other. As a result, a position of an upper surface of the element isolation portion formed between two fins adjacent to each other and a position of an upper surface of the element isolation portion STI formed between the fin closest to the dummy fin and the dummy fin is lower than a position of an upper surface of the element isolation portion STI formed in a shunt region.

Semiconductor device and method for manufacturing the same

In manufacturing a trench type MOSFET, reliability of a semiconductor device is prevented from being degraded due to a short circuit or lowering of withstand voltage between a trench gate electrode and a source region. To achieve the above, poly-silicon films are formed inside a trench in a main surface of a semiconductor substrate and over the semiconductor substrate. Further, phosphorus is thermally diffused into each poly-silicon film from a phosphorous film over an upper surface of the poly-silicon film. Still further, a silicon oxide film formed in a surface layer of the poly-silicon film by the thermal diffusion process is removed by a first dry etching process using a fluorocarbon gas or a hydroxy-fluorocarbon gas. Then, by performing a second dry etching process using a Cl2 gas etc., an insulating film is exposed and, thereby, a trench gate electrode including the poly-silicon film is formed.

Method of manufacturing semiconductor device

A semiconductor device with enhanced reliability in which a gate electrode for a trench-gate field effect transistor is formed through a gate insulating film in a trench made in a semiconductor substrate. The upper surface of the gate electrode is in a lower position than the upper surface of the semiconductor substrate in an area adjacent to the trench. A sidewall insulating film is formed over the gate electrode and over the sidewall of the trench. The gate electrode and the sidewall insulating film are covered by an insulating film as an interlayer insulating film.

A method of manufacture of a semiconductor device includes forming a gate insulating film and gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSilayer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.

Manufacturing method of semiconductor device

A method of manufacture of a semiconductor device includes forming a gate insulating film and a gate electrode made of polycrystalline silicon over a semiconductor substrate; implanting ions into the semiconductor substrate to form a semiconductor region as a source or drain; forming a cobalt film and a titanium nitride film over the semiconductor substrate to cover the gate electrode; carrying out annealing to cause a reaction between Co and Si and the semiconductor region to form a CoSi layer; carrying out wet cleaning to remove the titanium nitride film and unreacted cobalt film to leave the CoSi layer over the gate electrode and semiconductor region; carrying out annealing to cause a reaction between the CoSi layer and the gate electrode and semiconductor region to form a CoSilayer; carrying out HPM cleaning; and forming over the semiconductor substrate a silicon nitride film by low-pressure CVD to cover the gate electrode.

In a high-performance semiconductor integrated circuit, the standby current is reduced by preventing current leakage in a semiconductor integrated circuit device, for example, the memory cell of an SRAM. A gate electrode G is formed on semiconductor substrateand n-type semiconductor regions(source/drain regions) are formed in the semiconductor substrate on both sides of this gate electrode. Within the same apparatus and under near-vacuum conditions, a depth of 2.5 nm or less is etched away from the surfaces of the source/drain regions and gate electrode, a film of Co is then formed on the source/drain regions, and thermal processing is applied to form CoSilayer. As a result, current leakage in the memory cell can be prevented and this method can be applied to semiconductor integrated circuit devices that have low current consumption or are battery-driven.

Growing community of inventors

Hitachinaka, Japan

Katsuhiro Uchimura