Panasonic Corporation

Katsuhiro Otani

Kyoji Yamashita

Katsuya Arai

Daisaku Ikoma

Gate electrodesA throughF are formed to have the same geometry, and protruding parts of the gate electrodesA throughF extend across an isolation region onto impurity diffusion regions. The gate electrodeB and P-type impurity diffusion regionsBare connected through a shared contactAto a first-level interconnect MH, and the gate electrodeE and N-type impurity diffusion regionsAare connected through a shared contactAto a first-level interconnect MI. In this way, contact pad parts of the gate electrodesA throughF can be located apart from active regions of a substrate for MOS transistors. This suppresses the influence of the increased gate length due to hammerhead and gate flaring. As a result, transistors TrA through TrF can have substantially the same finished gate length.

Growing community of inventors

Nara, Japan

Katsuhiro Otani