Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Katsuhiro Ootani

Kyoji Yamashita

Daisaku Ikoma

Yasuyuki Sahara

Shiro Sakiyama

Masayoshi Kinoshita

Katsuji Satomi

Jun Kajiwara

Shinsaku Sekido

Atsuhiro Kajiya

Kazuhisa Nakata

Katsuya Arai

Ken Suzuki

Nobuyuki Tamura

Toshihiro Kogami

Shinji Watanabe

Tomoyuki Ishizu

Hiroo Yamamoto

A semiconductor device includes a first MIS transistor on a first active region of a semiconductor substrate, the first MIS transistor including: a first gate insulating film provided on the first active region; a first gate electrode provided on the first gate insulating film; a first stressor insulating film provided on an upper face and side faces facing in a gate length direction of the first gate electrode such that first stress acts on a channel of the first MIS transistor in the gate length direction; and a first base insulating film provided on side faces of the first gate electrode facing in a gate width direction, wherein the side faces of the first gate electrode facing in the gate width direction are not covered with the first stressor insulating film.

Semiconductor device and fabrication method thereof

A circuit simulation apparatus has a means to acquire data regarding a transistor, a model parameter generation unit for generating a model parameter representing effects of stress upon the transistor active region caused by the isolation region, and a simulation execution unit for evaluating characteristics of the transistor using a simulation program associated with the model parameter. The model parameter includes a term regarding width of the transistor active region, a term regarding width of the peripheral active region, and a term regarding width between the transistor active region and the peripheral active region.

Circuit simulation method

A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Semiconductor device

In a cell comprising an N well and a P well, a distance SPfrom a center line of a contact N-type region to an N well end of the N well is set to be a distance which causes a transistor not to be affected by resist. A distance from a well boundary to the center line of the contact N-type region is equal to SP. A design on the P well is similar to that on the N well. Thereby, modeling of the transistor in the cell can be performed, taking into consideration an influence from resist in one direction. Also, by fabricating a cell array which satisfies the above-described conditions, design accuracy can be improved.

Mask layout design improvement in gate width direction

An integrated circuit includes: a first well of a first conductivity type; a second well of a second conductivity type coming into contact with the first well at a well boundary extending in a gate length direction; a first transistor having a first active region of the second conductivity type provided in the first well; and a second transistor which has a second active region of the second conductivity type provided in the first well and differing from the first active region in length in a gate width direction. The center location of the first active region in the gate width direction is aligned with the center location of the second active region in the gate width direction with reference to the well boundary.

Semiconductor integrated circuit

A first PMIS transistor includes a first active region which is formed on a semiconductor substrate and a first gate electrode which is formed on the first active region and which is connected at one end thereof to a first gate wiring and includes at the other end thereof a first protruding portion protruding at a side opposite to the first gate wiring side from the first active region A first NMIS transistor includes a second active region which is formed on the semiconductor substrate with a space left from the first active region and a second gate electrode which is formed on the second active region and which is connected at one end thereof to the first gate wiring and includes at the other end thereof a second protruding portion protruding at a side opposite to the first gate wiring side from the second active region. A protruding length of the first protruding portion of the first PMIS transistor is greater than a protruding length of the second protruding portion of the first NMIS transistor.

Semiconductor circuit device and simulation method of the same

An inventive semiconductor circuit device includes an N-well and a P-well. The N-well is provided with PMIS active areas surrounded by a trench isolation, and the P-well is provided with NMIS active areas surrounded by the trench isolation. The PMIS active areas are each provided with a gate of a P-channel transistor, and the NMIS active areas are each provided with a gate of an N-channel transistor. A layout is designed such that a distance Dpn between the NMIS active areas and the PMIS active areas in a Y-direction substantially becomes a fixed value. Thus, trench isolation stresses applied from the trench isolations to channel regions under the gates become uniform for respective transistors, resulting in an improvement in accuracy of circuit simulation.

Semiconductor circuit device and circuit simulation method for the same

An electrostatic discharge protected transistor of the present invention includes transistors in an active region composed of a p-type semiconductor substrate and surrounded by element isolation regions. On the active region composed of the p-type semiconductor substrate, an on-source silicide film and an on-drain silicide film are provided. The on-drain silicide film is not provided in a portion located on a boundary of each transistor and divided to correspond to the respective transistors. As a result, regions between respective pairs of the transistors have high resistances, and it is, therefore, possible to prevent a current from flowing between the different transistors and prevent local current concentration. It is thereby possible to allow the electrostatic discharge protected transistor to make most use of an electrostatic destruction protection capability per unit area without increasing an area of the transistor.

Gates of pMISFETs which need high current driving capability are high-driving-capability gates placed in discontinuous active regions or high-driving-capability gates disposed in two-input active regions. Gate of pMISFETs which do not need high current driving capability are normal gates arranged in continuous active regions. Since the high-driving-capability gates are provided in the discontinuous active regions or the two-input active regions, pMISFETs with high driving capability is achieved by utilizing light holes created due to a lattice distortion.

Semiconductor device comprising a discontinuous region and/or a continuous region having trench isolation stress applied thereto

In a switching regulator, switching noise is reduced with keeping high conversion efficiency. The switching regulator includes plural output switching transistors through having different on-resistances, which are operated nadescending order of on-resistance in the on operation and are operated in an ascending order of on-resistance in the off operation. In this manner, abrupt current change can be suppressed in the switching operation, resulting in reducing di/dt noise derived from a parasitic inductor

Switching regulator and LSI system

The switching regulator of a synchronous rectifying mode comprises the first and second switches SW,, SW,arranged in series between the power source Vdd and the ground Vss, the switch control unit,which controls the on-off operation of the switches SW,, SW,, and the smoothing circuit,which smoothes the output node potential Vnd. When the signal Sc,indicates that the output node potential Vnd goes below the first reference potential Vr,which is the reference to detect the occurrence of the inrush current while the first switch SW,is in the ON state, the control circuit,turns off the first switch SW,. Thus, the detection of the inrush current is conducted by making use of a voltage drop due to the on resistance of the first switch SW,, so that it is unnecessary to provide a resistance element for detecting the inrush current.

Switching regulator DC/DC converter, and LSI system provided with switching regulator

A power circuit including means for preventing the generation of an inrush current during the power circuit's initial operation without increasing the size of the power circuit is described. The power circuit comprises an output transistor for supplying a current from a power supply to an output terminal, and a differential amplifier for controlling the current supplied by the output transistor in such a manner as to regulate a voltage at the output terminal based on a preset reference voltage. A limiting transistor is provided as a source follower on a current path at the output stage of the differential amplifier. The gate potential of the output transistor is controlled using the source potential of the limiting transistor. Before the power circuit starts to operate, an operation controller charges a capacitor to control the gate potential of the limiting transistor so that during the initial operation of the power circuit, the capacitor is discharged by using a current source. Accordingly, during the initial operation of the power circuit, the gate potential of the limiting transistor gradually decreases while the gate-source voltage of the output transistor gradually increases. As a result, the generation of the inrush current can be suppressed.

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Nara, Japan

Katsuhiro Ootani