Nec Corporation

Nippon Electric Co., Ltd.

Kaken Pharmaceutical Company, Ltd.

Kokusai Denshin Denwa Co., Ltd.

Katsuhiro Nakamura

Eiji Okamoto

Yukio Miyazaki

Masahide Nomura

Hideo Sugawara

Machiko Sugiyama

Ryusuke Taguchi

Yasuhiko Hamazaki

Akiya Furuichi

Goro Yabuta

Hideo Saito

Taku Mizuno

Shuji Murakami

Yukitsuna Furuya

Seiichi Noda

Yasuo Hirata

Yutaka Yasuda

In order to produce first and second Lee-error correcting code sequences in a multilevel quadrature amplitude modulator comprising a code converting unit (10) for converting first and second 2.sup.m -level input digital signals into first and second major converted signals by rearranging a square signal point arrangement into an approximately circular arrangement on a phase plane, each of the first and the second major converted signals consisting of m binary bits numbered from a first (least significant) bit through an m-th (most significant) bit, a first error correcting code producing circuit (21) carries out error correcting calculation for the first through an n-th bits of the first major converted signal to produce the first Lee-error correcting code sequence where n represents an integer which is not less than two and is not less than m. Similarly, a second error correcting code producing circuit (22) produces the second Lee-error correcting code sequence. The first and the second major converted signals are multiplexed with the first and the second error correcting code sequences into first and second major multiplexed signals, respectively. The first and the second major multiplexed signals are modulated into a multilevel quadrature amplitude modulated signal. In a counterpart multilevel quadrature amplitude demodulator, an inverse operation is carried out to produce the first and the second input digital signals.

Multilevel quadrature amplitude modulator capable of reducing a maximum

Substance F-0368 of the formula: ##STR1## or salts thereof is prepared by culturing Kitasatosporia sp. F-0368 in a culture medium thereby producing substance F-0368, and then isolating and collecting substance F-0368 from the culture medium.

Novel substance for agricultural use

Disclosed in the present invention are: a substance F-0368 or salts thereof having the following structural formula ##STR1## a method for production of the substance F-0368 or salts thereof, wherein an F-0368-substance-producing-microorganism belonging to a genus Kitasatosporia is cultured, and the substance F-0368 is isolated and collected from the cultured substance; a method for production of the substance F-0368 or salts thereof, wherein 3-methyl-4-lower alkoxy carbonyl-2(5H)-furanone represented by the following general formula is subjected to hydrolytic reaction ##STR2## (where: R represents a straight or branched lower alkyl group having 1 to 6 carbon atoms); a composition which consists essentially of the substance F-0368 or salt thereof, a diluent permissible in the agricultural chemicals, and a carrier or an excipient; a preventive agent for plant diseases such as rice blast disease and bacterial leaf blight disease, which consists essentially of an effective amount of the substance F-0368 or salts thereof as the active component, a diluent permissible in the agricultural chemicals, and a carrier or an excipient; a method for preventing plant diseases, wherein plants are treated with the preventive agent; a disinfectant for agricultural use to prevent plant disease such as rice blast disease and bacterial leaf blight disease, which consists essentially of an effective amount of the substance F-0368 or salts thereof, as the active component, a diluent permissible in the agricultural chemicals, and a carrier or an excipient; materials for agricultural use containing therein the substance F-0368 or salts thereof; a method for growing plants, wherein the plants are cultivated by use of the agricultural materials; and an F-0368-substance-producing microorganism (Kitasatosporia sp. F-0368; FERM BP-2259).

Lactone compound of agricultural utility

A data converter applicable to data communications protects messages against errors and modifications by a third party. What is required for the detection of errors and modifications is simply causing a transmit station to add a particular pattern and a receive station to detect the particular pattern.

Data encryptor

A cryptographic system comprises a modulo-2 adder having a first input receptive of a sequence of binary digits to be scrambled and a second input receptive of a sequence of scrambling binary digits for generating a sequence of scrambled binary digits. A function generator having a memory is provided for storing a predeterminable sequence of binary digits in addressible storage locations and reading the stored binary digits in response to an address code represented by combined first and second patterns of binary digits which are generated respectively by a random pattern generator and a shift register which is connected to the output of the modulo-2 adder. The output of the function generator is the scrambling binary digits applied to the modulo-2 adder.

Cryptographic system

An enciphering key distribution system comprises a transmitter having an address generator for generating the addresses of those subscribers to which a first enciphered TV signal is to be distributed. An enciphering generator generates a second enciphering, in response to the individual addresses, on a one-to-one correspondence with the individual subscribers. A multiplier produces a product which is associated with all the subscribers. An adder adds the first enciphered signal to the product. The system also comprises a receiver having a divider for dividing the signal transmitted from the transmitter by one of the second encipherings on a basis which is assigned to the particular subscriber or receiver.

Enciphering key distribution system for subscription TV broadcast or

Disclosed is an error correction system in which part of the data bits of first multilevel input data is differentially encoded to form second data comprising the differentially encoded data bits and the remainder data bits and converting the bit patterns of the second data into third data in two-dimensional multilevel signal space according to a predetermined transfer function. A transparent error-correcting code is derived from each of the different phases of the third data and appended to each different phase to thereby form fourth data which is then modulated upon a carrier in two-dimensional multilevel signal space for transmission to a receiver where the signal is demodulated to recover the fourth data. The appended error-correcting code is separated from each different phase of the fourth data. An error which might exist in the received data is corrected by the separated error-correcting code in respect of each phase. The bit pattern of the error-corrected data is reconverted to recover the original second data. One of the phases of the second data is differentially decoded to recover the original first data.

Error-correction system for two-dimensional multilevel signals

A Viterbi decoder synchronization circuit comprises a circuit that derives a word synchronization signal from a received bit stream of convolutional codes. A first detector detects a maximum of metric values derived from the Viterbi decoder at different locations in time. A memory is provided for storing therein the address codes derived at different times and the maximum metric values detected by the first detector. A second detector is connected to the memory for detecting the presence of a path between the states addressed by the address codes stored in the memory. An integrator is connected to the second detector to integrate its output signal. To the integrator is connected a third detector which detects when the integrator output reaches a value indicative of one of word-in-sync and word-out-of-sync conditions of the Viterbi decoder. A phase shift signal is generated in response to an output signal from the third detector and applied to a phase shifter to introduce a delay time to the bit stream.

Synchronization circuit for a Viterbi decoder

An encrypting device for an input data bit sequence comprises a shift register for producing a bit pattern represented by successive encrypted bits for the data bits preceding a current bit. A bit pattern converter selects in compliance with the bit pattern a bit of a code pattern preset therein. A keying bit may be provided by the selected bit, to which the current bit is added modulo two to produce a new encrypted bit. For more excellent encryption, the successively selected bits may be used to produce an additional bit pattern, responsive to which either the keying bit or an additional keying bit, to be also added to the current bit, may be provided by a selected bit of another code pattern. Each bit pattern converter may be preset with a plurality of code patterns. One or more encrypting devices may be used in encrypting a sequence of input data digits, each comprising a plurality of input data bits among which at least one bit may be a dummy bit. A decrypting device should have a structure corresponding to the counterpart encrypting device.

Device for encrypting each input data bit by at least one keying bit

An error correcting system for DPSK is comprised of an encoder unit, a decoder unit and a transmission medium disposed between the encoder and decoder units. The encoder includes a differential encoder for differentially encoding an input data sequence, an error correcting encoder for adding a check digit sequence to the differentially encoded data sequence, and a differential decoder for differentially decoding the data sequence added with the check digit sequence. The decoder unit includes a differential encoder for differentially encoding a received data sequences, an error correcting decoder for correcting error digits contained in the differentially encoded received data sequence, and a differential decoder for differentially decoding the output data sequence from the error correcting decoder. The transmission medium typically includes a differentially encoded phase-shifting-keying modulator unit and a differentially encoded phase-shift-keying demodulator unit.

Error correction system for differential phase-shift-keying

A parallel-processing error correction system for digital data transmission employing a code-polynomial division circuit having a serial-type shift register for a cyclic code. Provided with null input lines, one for each data input line, a set of switches for selection between the data and null input lines, and another set of switches associated with buffer registers for series connection therebetween, the device can be readily adapted for any change in number of parallel input bits by switch operation.

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Tokyo, Japan

Katsuhiro Nakamura