Kabushiki Kaisha Toshiba

Tokyo Electron Limited

Katsuhiro Ishida

Makoto Hasegawa

Katsuya Ito

Ryoji Matsushima

Hiroshi Sugiura

Seiichi Mori

Hiroaki Hazama

Tadashi Iguchi

Hiroaki Tsunoda

Takashi Kondo

Takashi Imoto

Hirohisa Iizuka

Mitsuhiro Nakao

Junya Sagara

Kenta Yasuda

Kazuhiro Yamamori

Naoto Takebe

Noboru Okane

Yuichi Sano

Yasushi Kumagai

Toru Kubota

Tomomi Honda

A plasma processing method according to an aspect includes: preparing a plasma processing apparatus including: a chamber; a lower electrode; an upper electrode; a focus ring surrounding a peripheral edge of the lower electrode; and an annular coil disposed on an upper portion of the upper electrode at a more outer position than the peripheral edge of the lower electrode; placing a substrate on the lower electrode, with a peripheral edge of the substrate surrounded by the focus ring; introducing process gas into the chamber; generating plasma of the process gas by applying high-frequency power across the upper electrode and the lower electrode; and leveling an interface of a plasma sheath on an upper portion of the substrate with that on an upper portion of the focus ring by generating a magnetic field by supplying a current to the annular coil.

Plasma processing method and plasma processing apparatus

According to one embodiment, a semiconductor device includes a first semiconductor element, a first electrode, a ball part, a second electrode, and a wire. The first electrode is electrically connected to the first semiconductor element. The ball part is provided on the first electrode. The wire connects the ball part and the second electrode. A thickness of a turned-back portion at an end of the wire on a side opposite to the second electrode is smaller than a diameter of the wire.

Semiconductor device, method for manufacturing semiconductor device, and manufacturing apparatus for semiconductor device

A wire bonding method involves bonding a wire in order at a first bonding point and a second bonding point; raising a capillary, through which the wire is inserted, on the second bonding point; cutting the wire by closing a clamper provided above the capillary at a time when the capillary has reached a prescribed height; and measuring a load incurred on the wire at a time of cutting of the wire.

Wire bonding apparatus and wire bonding method

A stacked semiconductor device includes a first semiconductor element mounted on a circuit substrate and a second semiconductor element stacked on the first semiconductor element via a spacer layer. An electrode pad of the first semiconductor element is electrically connected to a connection portion of the circuit substrate through a first metal wire. A vicinity of the end portion of the first metal wire connected to the electrode pad is in contact with an insulating protection film which covers the surface of the first semiconductor element.

Stacked semiconductor device and method of manufacturing the same

A stacked semiconductor device includes a first semiconductor element mounted on a wiring board and a second semiconductor element stacked on the first semiconductor element. Electrode pads of the first and second semiconductor elements are electrically connected to connection pads of the wiring board via first and second metal wires. The second metal wire is wired so that a part thereof is in contact with an insulating protective film covering a surface of the first semiconductor element.

Stacked semiconductor device and semiconductor memory device

A semiconductor device comprises a non-volatile memory including a memory cell array, element isolating regions, a second trench and a word line. The memory cell array is constituted by memory cells which have floating electrodes and are arranged in the shape of a matrix on a semiconductor substrate. Each of the element isolating regions has a first trench formed in the semiconductor substrate and between memory cells adjacent to each other along a gate width direction, and an isolating filler filled in the first trench. The second trench is formed in the isolating filler and between the floating electrodes of the memory cells adjacent to each other along the gate width direction, and is narrow at the bottom thereof. The word line is connected to the memory cells, buried in the second trenches and extending along the gate width direction.

Semiconductor memory preventing an electric short circuit between a word line and a semiconductor substrate, and manufacturing method for the semiconductor memory

A stack-type semiconductor device according to the present invention includes a circuit board with bonding pads; a first semiconductor chip which includes first electrode pads and is mounted on the circuit board; a second semiconductor chip which includes second electrode pads and is mounted on the first semiconductor chip; a plurality of bonding wires sequentially connecting the bonding pads, the first electrodes and the second electrodes as a whole; and a sealing resin for sealing the first semiconductor chip, the second semiconductor chip and the bonding wires.

Multi-stack chip package with wired bonded chips

A semiconductor device includes a semiconductor substrate, a lower wiring layer formed on the semiconductor substrate, a first interlayer insulating film formed on the lower wiring layer and including a first upper surface and a second upper surface, the first upper surface being higher than the second upper surface relative to a surface of the semiconductor substrate, a contact plug formed in the interlayer insulating film and including a first bottom surface contacting to the lower wiring layer, a third upper surface flush with the second upper surface and a fourth upper surface flush with the first upper surface, an upper wiring layer formed on the first and third upper surfaces and including a first side surface and a second side surface opposite to the first side surface, and a second interlayer insulating film formed on the second and fourth upper surfaces.

Semiconductor device having multilayer wiring structure

A method of fabricating a semiconductor device includes forming a lower wiring layer on a semiconductor substrate, forming an interlayer insulating film on the lower wiring layer, layer, forming a plurality of. contact plugs in the interlayer insulating film so that the contact plugs are brought into electrical contact with the lower wiring layer, thereby forming an interlayer wiring layer, forming an upper wiring, layer on the interlayer wiring layer so that the upper wiring layer is brought into electrical contact with the contact plugs, and patterning the upper wiring layer so that the upper wiring layer corresponds to the contact plugs. In the patterning, after the upper wiring layer has been etched, the exposed interlayer insulating film and the exposed contact plugs are etched.

Growing community of inventors

Yokkaichi, Japan

Katsuhiro Ishida