Toshiba Memory Corporation

Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Information Systems (japan) Corporation

Katsuhiko Ueki

Yoshihisa Kojima

Hiroyuki Nemoto

Kazuya Kitsunai

Wataru Okamoto

Makoto Kuribara

Daisuke Hashimoto

Shigehiro Asano

Takeshi Yasuda

Tatsuya Zettsu

Sumio Kuroda

Yasuyuki Ozawa

Masato Igarashi

Shinichiro Nakazumi

Noriaki Koyama

Mark Hayashida

Humitaka Tamura

Masayuki Hirayama

Masanobu Shirakawa

Hiroshi Yao

Kenichiro Yoshii

Takeshi Tomizawa

Kiyotaka Iwasaki

Kouji Watanabe

Ikuo Magaki

Yusuke Ochi

Kenichiro Suzuki

Mitsuhiko Sugiyama

Atsuo Shono

Ikuya Odahara

Tomoko Nishimura

Akiyoshi Hashimoto

Masaaki Okajima

In a memory system in an embodiment, in a case of normal operation, a control unit returns a write completion response upon completion of reception of write data from a host, and writes the write data into nonvolatile memory in a multiple values. In a case of unordinary power-off, changeover to operation using a backup battery is conducted and the control unit writes dirty data that is not completed in writing into the nonvolatile memory, into the nonvolatile memory with two values. When next boot, the control unit reads the dirty data from the nonvolatile memory into the volatile memory, and thereafter writes the dirty data into the nonvolatile memory in a multiple values.

Memory system and controller

According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a plurality of storage areas. Each of the storage areas includes a plurality of memory cells to which threshold voltages are set in accordance with data. The controller acquires a first threshold voltage distribution of memory cells in a first storage area of the storage areas. The controller acquires a second threshold voltage distribution of memory cells in a second storage area of the storage areas. The controller detects non-normalcy in the first storage area or the second storage area from a first divergence quantity between the first threshold voltage distribution and the second threshold voltage distribution.

Memory system and method

A storage device includes a nonvolatile memory including a plurality of physical blocks, a communication interface connectable to a host, and a controller. The controller is configured to generate metadata of host data, which include user data and metadata of the user data, and write, in a physical block of the nonvolatile memory, the metadata of the host data, the metadata of the user data, and the user data continuously in this order, when the host data are received through the communication interface in association with a write command.

Reconstruction of address mapping in a host of a storage system

According to one embodiment, a storage device includes a first memory cell; a second memory cell; and a controller configured to, in response to receiving a first command set, execute a first erase operation which is included in an erase operation of data of the first memory cell, and suspend the first erase operation, and in response to receiving a second command set, execute a read operation or a write operation of the second memory cell and subsequently resume the suspended first erase operation.

Storage device

A memory system includes a plurality of memory cells and a controller. During a write operation to write data to the memory cells, the controller encodes first data to be written at a first code rate. During a read operation to read data from the memory cells, the controller decodes second data read from the memory cells at the first code rate. The controller changes the first code rate to a second code rate that is less than the first code rate upon determining that the number of error bits during the read operation of the second data is above a threshold number for error bits or upon determining that the number of memory cells having a threshold voltage that is in a voltage range that includes a read voltage is above a threshold number for memory cells.

According to one embodiment, a memory system is provided with a nonvolatile memory, a controller, a volatile memory and an address translation table. The address translation table includes a high level and a plurality of low levels. The high level indicates positions in the nonvolatile memory in which the low levels are recorded. The low levels indicate positions in the nonvolatile memory in which data is recorded. The controller holds the high level of the address translation table in the first area of the volatile memory, and shuts off the supply of power to the second area of the volatile memory based on a transition from a normal-power state to a low-power state.

Reduction of power use during address translation via selective refresh operations

According to one embodiment, a memory system includes a memory, an error correcting circuit and a memory controller. The memory includes a memory cell which is writable in a memory mode including a first mode and a second mode. The first mode is a mode in which a value of bits is written to the memory cell. The second mode is a mode in which a value of bits smaller than that in the first mode is written to the memory cell. The memory controller controls a coding rate for the error correction on the basis of result of error correction. The controller sets the first mode as the memory mode to be used. The controller changes the memory mode to be used from the first mode to the second mode in a case where the coding rate is less than a first threshold.

Memory system and control method

According to one embodiment, a memory system includes a nonvolatile memory, and a controller configured to control the nonvolatile memory. The controller includes an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from an outside, and a processor configured to execute a background process for the nonvolatile memory, based on a second request which is issued from the outside before the first request is issued.

Memory system and information processing system utilizing space information

According to one embodiment, a controller executes a first process such that writing is performed in an order of page numbers in the memory chip. The first process includes a second process to be executed in an order of group units. The second process includes a process of writing data to the lower pages of the memory chips belonging to the banks in one group, and subsequently writing data to the upper pages of the memory chips belonging to the banks in the group.

Memory system controlling interleaving write to memory chips

According to one embodiment, a memory system includes a semiconductor memory and a memory controller. The memory controller writes a first data group in the semiconductor memory and then reads the first data group from the semiconductor memory. The memory controller counts a number of first data and a number of second data based on a comparison of a second data group with a third data group. The memory controller changes a first charge threshold based on the number of first data and the number of second data. The second data group is the first data group at the time of writing to the semiconductor memory. The third data group is the first data group read from the semiconductor memory. The first data is data changed from a first code to a second code. The second data is data changed from the second code to the first code.

Memory system

According to one embodiment, a memory system includes a memory, and a processor. The memory converts an amount of charge held by a memory cell into a value. The processor executes a first process of reading first data from the memory. The processor executes a second process of reading the first data by making the memory use a first determination potential different in a case where error correction of the first data read through the first process is failed. The processor executes a third process of reading second data from the memory by making the memory use a third determination potential in a case where error correction of the first data read through the second process is succeeded. The third determination potential is the first determination potential used by the memory in a case where error correction of the first data read through the second process is succeeded.

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Tokyo, Japan

Katsuhiko Ueki