Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Katsuhiko Ueda

Minoru Okamoto

Toshihiro Ishikawa

Mikio Sakakihara

Shinichi Marui

Shirou Yoshioka

Tetsuji Kishi

Toshio Sugimura

Masayuki Yamasaki

Norihito Kinoshita

Toshikazu Suzuki

Mikako Yasutome

Hiroyuki Yasoshima

A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits a license request for using a function standard required for realizing the function to a license management device. The license management device receives the usage license request and correspondingly transmits an authorization for using the function standard to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device only when the usage authorization is received. The contents distribution device transmits the information contents to the terminal device only when the usage authorization is received.

Information contents download system

An information processing method for coding a program to enable an information processing device having an instruction decoder having a reconfigurable circuit, comprises the steps of: simulating execution of the program to obtain a history of instructions executed; extracting a routine in which a number of types of codes used in at least a field among fields constituting an instruction is limited to a predetermined number or less, from the program based on the history; inserting an instruction for changing circuit configuration of the reconfigurable circuit at start and end of the routine; allocating codes so that number of times of change of bit values in a field in which the number of types of codes used are limited is reduced for the routine; and converting a program obtained in the step of inserting an instruction to codes according to the allocation for the routine.

Inserting decoder reconfiguration instruction for routine with limited number of instruction types recoded for reduced bit changes

An information processing device for sequentially reading and executing programs stored in memory means, including: a program counter for outputting an address for reading a program to the memory means; an instruction decoder for decoding instructions read from the memory means in response to a control signal indicating a period in which the types of codes used in at least a field among fields constituting an instruction in the program are limited to a predetermined number or less; and controlled means for performing processing corresponding to the decoded results output from the instruction decoder. The instruction decoder has a reconfigurable circuit for changing the circuit configuration in response to the control signal so that the decoding is performed based on a relationship between codes in a field in which the types of codes used are limited and decoded results, the relationship being set so that the number of times of change of bit values in the field is reduced.

Information processing apparatus and information processing method

A multiprocessor includes M banks storing a plurality of instructions; and N processors each having N instruction fetch stages, wherein each of the N processors processes one of the plurality of instructions in a pipelined manner, where N is an integer equal to or greater than 2, and M is an integer equal to or greater than N, wherein each of the N processors fetches one of the plurality of instructions at a different instruction fetch stage from instruction fetch stages used by other processors.

Multiprocessor with asynchronous pipeline processing of instructions, and control method thereof

A data transfer device connected to a bus and a control signal line, includes: a judgment circuit for judging whether or not a state change of the bus, which occurs in a case where the data is manipulated to be output to the bus, is smaller than the state change of the bus, which occurs in a case where data is output to the bus without manipulating the data; a first manipulation circuit for manipulating the data in accordance with the result of judgment; a first output circuit for selectively outputting one set of the data and the data manipulated by the first manipulation circuit to the bus in accordance with the result of judgment; and a second output circuit for outputting a control signal indicating the result of judgment to the control signal line.

Data transfer device and data transfer method

This invention provides a code generator for reduction of the power consumption of digital signal processors. A plurality of codes are prepared for an item of data. A code with the lowest polarity-inverting bit count for input data, is selected from among the prepared codes. The code generator of the present invention has a code generation section, a code selection section and a code output section. The code generation section inputs data from a data file and generates all codes allocated to the input data. The code selection section makes a comparison between each of the generated codes and a code that is transferred just before or after any one of the generated codes is transferred over a bus of the digital signal processor, in order to select from among the generated codes a code having the lowest polarity-inverting bit count. The code output section writes the selected code into a code file. In addition, the code output section temporarily holds the selected code and outputs it to the code selection section as a comparison target code used to select the next code.

Data transmitter and method object code generator and method digital

A program control apparatus includes a memory for storing a REPEAT command to a first address, a calculation command such as sigma command to a second address after the first address, and another calculation command, such as a SUBTRACTION command to a third address after the second address. A repeat controller is operated in response to the REPEAT command for setting a repetition number. A first operation executor operates in response to the sigma command for executing the adding operation repeatedly by the repetition number. A second operation executor operates in response to the SUBTRACTION command for executing the subtraction in parallel to the adding execution in the first executor.

Program control method and program control apparatus

The present invention discloses a pipeline processor system comprising a pipeline processor and a memory device, wherein the memory device is comprised of a memory unit for holding data and/or an instruction as well as being accessed to implement memory read operation or memory write operation in a clock cycle; and a data latch unit for latching data to be written into the memory unit, while the pipeline processor is comprised of an instruction detection unit for detecting from fetched instructions a first predetermined instruction which directs the latch of the data as well as a second predetermined instruction which directs write of the data at the data latch means into the memory means; and a latch control unit for controlling to latch operation results of the first predetermined instruction to the data latch unit when the predetermined instruction is detected by the instruction detection unit as well as controlling to write the data at the data latch unit into the memory unit when the second predetermined instruction is detected. The first predetermined instruction includes operand fetch from the memory unit replaced with the latch of the operand, the operand fetch encompassing two memory accesses having been planned in a clock cycle together with the memory write operation; and the second predetermined instruction includes execution of an instruction and the write of the data at the data latch means into the memory means, the instruction placing after the first predetermined instruction and excluding its own memory access.

Pipeline processor which avoids resource conflicts

A shift operation unit includes: a shift means for shifting data in accordance with a shift count and outputting the most significant part bit data, intermediate bit data, and least significant part bit data; first selection means coupled to an output of the shift means, for selecting one of the most significant part bit data and the least significant part bit data in accordance with a shift direction; first storage means coupled to an output of the first selection means, for storing data selected by the first selection means; operation means coupled to an output of the shift means and an output of the first storage means, for operating the intermediate bit data and the data stored in the first storage means and outputting an operation result; and second storage means coupled to an output of the operation means, for storing the operation result. A shift operation method is also provided.

Shift operation unit and shift operation method

An interleaving memory system having a first memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, a second memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, and a holding device for holding data from one of the banks of one of the first memory device and the second memory device to delay an output of the data for 1/2 cycle time for sequential addressing. A controller controls first and second selection devices wherein the 0-bank and the 1-bank are alternatively selected when data is outputted either in an ascending order of consecutive addresses from the even-numbered addresses in the first or second memory devices, or in a descending order of consecutive addresses from the odd-numbered addresses in the first or second memory devices. Also, the first holding device and a bank whose output is not held by the first holding device are alternatively selected when data is outputted either in a descending order of consecutive addresses from the even-numbered addresses in the first memory device, or in an ascending order of consecutive addresses from the odd-numbered addresses in the first memory device. The second holding device and a bank whose output is not held by the second holding device are similarly alternatively selected.

Interleaved memory wherein plural memory means comprising plural banks

In a digital signal processor, an arithmetic apparatus capable of performing Viterbi decoding processing at a high speed with minimum addition of hardware and least overhead of memory. Pathmetric value and branchmetric value read out from first and second memories on two paths are simultaneously added by an adder at most significant bits and least significant bits thereof. A comparator compares values of the most significant bits and the least significant bits output from the adder to generate a path select signal indicating the value which is pathmetrically smaller. The select signal is stored in a shift register on a bit-by-bit basis. Of the values of the most significant bits and the least significant bits of a register storing the output of the adder, the smaller one as decided by the path select signal is written in the memory at eight most significant bits or least significant bits thereof via distributor, a bus and a register.

Arithmetic apparatus for digital signal processor

A stored instructions executing type timing signal generating system for flexibly generating a plurality of control timing signals having many changing points includes an instruction memory for storing a series of instructions stating contents of changes and relative time intervals between the changes of a series of control timing signals and a circuit for triggering the instruction execution by the absolute time for the series of instructions, so that after a first instruction has been executed, each succeeding instruction is sequentially executed on the basis of a relative time interval before the execution of a next instruction stated in the instructions, thereby to generate the control timing signals. The number of changing points of the control timing signals is basically dependent only on the number of words of the instruction memory, and therefore the plurality of control timing signals having many changing points can be generated easily.

Stored instructions executing type timing signal generating system

A floating-point arithmetic apparatus includes a first device for matching scales of first and second floating-point data. A second device serves to perform addition and subtraction between outputs from the first device. A third device serves to normalize output from the addition/subtraction device. A fourth device serves to round off output from the third device. A fifth device serves to calculate an absolute value of output from the third device. The fourth device and the fifth device may include a common adder.

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Sakai, Japan

Katsuhiko Ueda