Fujitsu Corporation

Toshiba Storage Device Corporation

Katsuhiko Takeuchi

Hirohide Sugahara

Sumie Matsubayashi

Shinichi Utsunomiya

Nobuyuki Myouga

Kazunari Matsumoto

Shin-ichi Utsunomiya

Nobuyuki Myoga

Shini-chi Utsunomiya

A device interface circuit unit transfers a command and data in packet format between the unit and the host. A transport layer is provided with a receive FIFO, a command detection circuit and a send FIFO, and an application layer is provided with a receive task file register and a send task control file register. An available time is generated for each break point of a packet during data transfer in order to receive another command packet from the host. When the command packet is received from the host in the available time during data transfer, the data transfer is suspended and the received command is decoded to execute a process for continuing or canceling the data transfer, after which the data transfer is resumed.

Interface apparatus and packet transfer method

Information about an attribute of packets that are receivable corresponding to a command is registered. When a packet is received, information about an attribute of the packet received is acquired. Upon occurrence of a reception error that there is no information in the attribute registering unit corresponding to the information acquired by the attribute acquiring unit, a predetermined reception error handling routine is executed according to a type of the reception error.

Storage control apparatus, storage apparatus, storage control method, and computer-readable recording medium for executing a command based on data in received packet

A power saving of a serial interface circuit decreases the unnecessary power consumption of a serial interface circuit, while decreasing the return time and expanding the power saving range. Gates are disposed for stopping the clock supply to a digital portion of the interface circuit while maintaining operation of clock sources in the digital portions. Therefore a quick shift to and return from the power save mode by stopping and restarting clocks is implemented, which further decreases power consumption.

Serial type interface circuit, power saving method thereof, and device having serial interface

There is provided a data synchronization circuit for synchronizing a (n+1) (n: natural number) bit bus data synchronous with a first clock with a second clock, comprising: a first circuit for holding the bus data which is synchronous with the first clock and is input at each predetermined timing; a second circuit for generating a first timing signal which is synchronous with the first clock and is corresponding to the predetermined timing; a third circuit for generating a second timing signal which is synchronous with the second clock, from the first timing signal; and a fourth circuit for receiving the bus data output from the first circuit based on the second timing signal, to output the bus data in synchronism with the second clock.

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Kawasaki, Japan

Katsuhiko Takeuchi