Kabushiki Kaisha Toshiba

Toshiba Engineering Corporation

Katsuhiko Sato

Shinji Miyano

Tomoaki Yabe

Kenji Numata

Motohiko Kimura

Tohru Furuyama

Yutaka Togasawa

Hiroaki Igakura

Kiyofumi Ochii

Masataka Matsui

Ryo Haga

Yasuhiro Yuguchi

Masaki Yoda

Naruhiko Mukai

Yuji Sano

Kenji Kurihara

Katsuhiko Naruse

Yuuji Yasuda

Seiki Soramoto

Makoto Kondo

Makoto Ochiai

Hidehiko Kuroda

Keniti Imamiya

Mitsuaki Shimamura

Yoshifumi Sato

Masataka Tamura

Akira Sudo

Shigeki Maruyama

Wataru Kono

Mitsuhiro Enomoto

Muneyoshi Kikunaga

Takehisa Hino

Tooru Ootsubo

Noboru Jimbo

Takahiro Hamano

Yasumi Kitajima

Yoshimi Tanaka

Yukihiro Urakawa

Hidefumi Amanai

Seishi Shima

Toru Sakamoto

Toshinori Terashima

A vibration measuring apparatus for nuclear reactor internal structure includes a holder which has an opening contact on a surface of a pressure vessel of a nuclear reactor; a vibrator accommodated in the holder so as to transmit or receive an ultrasonic wave; a couplant with which the holder is filled up; and, a bias component applies a biasing force to the vibrator in the direction of the opening; The couplant is a solid state of metal material at normal temperature and change to liquid stage by heat transfer from the pressure vessel.

Vibration measuring apparatus for nuclear reactor internal structure and vibration measurement method therefor

A modular submersible repairing system includes a working unit having a tool module capable of repairing structures in a reactor. A scanning/pitching module is capable of being selectively connected to or disconnected from the tool module, and is provided with a scanning/pitching shaft for scanning or pitching the tool module. A submersible fan module is capable of being selectively connected to or disconnected from the scanning/pitching module. A first buoyant module keeps an orientation of the tool module. A base unit includes a manipulator module internally provided with an actuator driving mechanism. An adsorbing module is capable of being detachably mounted on the manipulator module and a wall. A second buoyant module keeps the orientation of the manipulator module. The scanning/pitching module and the manipulator module are provided with a submersible connecting device capable of being operated in water for engagement and disengagement.

Modular submersible repairing system and repairing method

A laser emitting head for irradiating a portion to be machined with laser beams outputted from a laser unit () incorporates an emitting head body having a light guide member () in the head for guiding the laser beams; a light converging lens () for converging the laser beams transmitted from the light guide member in the head; a reflecting mirror () for irradiating the portion to be machined with the converged laser beams; mirror rotating means () for holding the reflecting mirror to be rotative around the optical axis of the laser beam; distance-adjustment means () for adjusting the relative distance between the reflecting mirror and the converging lens; and moving means () for moving the reflecting mirror and the converging lens such that the relative distance is maintained so that the light guide member in the head. The converging lens and the reflecting mirror can be introduced/discharged with respect to a portion to be machined and formed in a narrow gap in an incore structure. As a result, a preventive-maintenance/repair operation using laser beams and arranged to be performed in a narrow gap in the incore structure can safely and efficiently be performed.

Laser emission head, laser beam transmission device, laser beam transmission device adjustment method and preventive maintenance/repair device of structure in nuclear reactor

Modular submersible repairing system

A laser maintaining and repairing apparatus including a laser oscillator 7, beam guiding apparatus 8 connected to guide a laser beam of the laser oscillator 7, and emitting head 12 for converging the laser beam from the beam guiding apparatus 8 and emitting the beam to a portion to be processed. The beam guiding apparatus 8 includes liquid-tight tubular beam guiding members 9a to 9h. The beam guiding members 9a to 9h are provided with reflecting members 13a, 13b and at least one of mechanisms 10a, 10b and 11a, 11b for providing horizontal turning, horizontal extending, vertical turning and vertical extending operations at the beam guiding members 9a to 9h. With the laser maintaining and repairing apparatus of the noted structure, a laser beam of high energy density can be utilized and processing by the laser beam can be facilitated or the applying range can be increased.

Laser maintaining and repairing apparatus

A semiconductor integrated circuit incorporating DRAM 2 and a logic circuit 3 includes a vector generating circuit 40 formed on the common substrate. Upon a burn-in process, the vector generating circuit 40 and a refresh counter and control circuit 23 are activated to generate addresses, commands and data required for activating DRAM 2. In this manner, DRAM 2 and the logic circuit 3 can be activated independently, simultaneously, and the time required for the burn-in process can be reduced.

Semiconductor integrated circuit

An LSI chip has a main surface occupied by a logic section, a data input/output section and a memory macro section. The memory macro section is a rectangular section arranged on the main surface of the LSI chip. A test control circuit is arranged along one side of the memory macro section. A data input/output circuit is arranged along another side of the memory macro section. The test control circuit may be arranged along one side of the LSI chip. Test data is supplied from the test control circuit to the data input/output circuit through a data bus. As a result, a load of designing a memory logic LSI can be lightened.

One-chip LSI including a general memory and a logic

When data stored in a memory cell of a memory cell array is written into cache memory, a write signal LW is set at an 'H' level. The write signal LW is input into a data-line pair initialization select circuit via an initialization control circuit, and a signal EQE is set at an 'H' level in all columns. A data-line pair initialization circuit then sets the potential of the data-line pairs in all columns at the same level. When the write signal LW is input to a transfer gate via a transfer gate control circuit, the transfer gates in all columns are turned ON. The delay time of the transfer gate control circuit is the same as or greater than the delay time of the initialization control.

Memory circuit with built-in cache memory

A semiconductor memory device includes a memory cell array, row decoder, bit line pairs, sense amplifier, sense amplifier control circuit, data latch, transfer gate, transfer gate control circuit, and write circuit. The memory cell array has dynamic memory cells arranged in an array form. The row decoder decodes a row address signal to select a desired one of rows of the memory cell array. Each of the bit line pairs is connected to those of the memory cells which are arranged on a corresponding one of columns of the memory cell array. The sense amplifier amplifies data read out on the paired bit lines and positively feeding data back to the paired bit lines to hold the data. The sense amplifier control circuit controls the operation of the sense amplifier. The data latch latches readout data and write data. The transfer gate transfers data between the data latch and the sense amplifier. The transfer gate control circuit controls the transfer gate. The write circuit writes data into the data latch in synchronism with a clock signal. At the time of writing data into the memory cells, data is previously supplied to the data latch by the write circuit and latched in the data latch, and after the transfer gate control circuit controls the transfer gate to supply data to the bit line pairs from the data latch, the sense amplifier control circuit activates the sense amplifier.

Clock synchronous type DRAM with latch

A semiconductor device of a memory-macro type can be designed within a short time to have a desired storage capacity, which does not occupy a large area, so as to reduce the chip cost. The semiconductor device includes a memory macro having sub-memory macros, each sub-memory macro having a DRAM memory-cell array, and a row decoder and a column decoder for selecting any desired memory-cell from the memory cell of the array. The memory macro also includes a control-section macro having a DC potential generating circuit for generating various DC potentials required to drive the sub-memory macros. At least one of the sub-memory macros is combined with the control-section macro to form the memory macro as a one-chip memory capable of storing an integral multiple of N bits.

Memory standard cell macro for semiconductor device

Clock synchronous type DRAM with data latch

According to the present invention, a data bus common to a plurality of memory cell arrays is formed by selecting a column so as to prevent a data collision from occurring. Specifically, two memory cell arrays have each of data buses in common. A column decoder is supplied with a control signal to control a column selection logic circuit. The column selection logic circuit is so controlled that the data read out to the data buses in response to the control signal is prevented from colliding with each other during the simultaneous access to the two cell arrays.

Semiconductor memory circuit having data buses common to a plurality of

A data register that stores the data corresponding to the selected memory cell in a memory cell array is provided near the memory cell array. A decoder that selects the data from the data register starts decoding in response to an address signal accessing the memory cells in synchronization with a clock signal determining the operation period. In the first half of an operation period of the clock signal, the decoder outputs a signal in response to a signal corresponding to the address signal determined in the preceding operation period. According to the output of the decoder, the data register is selected. In the latter half of the operation period, a signal corresponding to a new address signal for the next operation period is transferred to the decoder. By doing this, the output control signal in the decoder is caused to synchronize with a signal driving an address signal, enabling the proper address to be selected without fail.

Semiconductor memory device with a decoding peripheral circuit for

A semiconductor memory device comprises column decoders of the number greater than the number of column addresses of a memory cell array and logical circuits of the same number as that of the column addresses. A column gate of a column is controlled by means of a logical OR between outputs from a plurality of column decoders for decoding different column addresses. As a result, even a column located at an end of the memory cell array can be accessed by means of a logical OR between outputs from a column decoder corresponding to the column and another column decoder.

Semiconductor memory device having a column selector

A semiconductor memory device including dynamic memory cells for which refresh operation is required, wherein one fundamental cycle consists of a normal operation for carrying out writing or reading into or from the memory cells and a refresh operation. This semiconductor memory device comprising: a refresh signal generating circuit supplied with a clock signal to generate a refresh signal indicating start of refresh; a count signal generating circuit supplied with the clock signal to generate a count signal required for selection of a memory cell to be refreshed, a refresh counter circuit supplied with the refresh signal and the count signal to select a word line and a bit line to which a memory cell to be refreshed is connected; and a precharge circuit supplied with the refresh signal to carry out precharge of the bit line for refresh.

Semiconductor memory device having refresh circuits

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Yokohama, Japan

Katsuhiko Sato