Kabushiki Kaisha Toshiba

Katsuhiko Oyama

Chiaki Takubo

Takashi Yamazaki

Takashi Imoto

Mitsuyoshi Endo

Hideo Aoki

Hiroshi Iwasaki

Masayuki Miura

Taku Nishiyama

Naohisa Okumura

Junichi Asada

Takahito Nakazawa

Yumiko Ohshima

Toshitsune Iijima

Hideo Taguchi

Mikio Matsui

Katsuya Sakai

Hideaki Maeta

Hiroshi Shimoe

Toshikazu Mino

Jun Omori

According to one embodiment, a semiconductor module has a substrate, two nonvolatile memories disposed on a first surface of the substrate, a controller to control the nonvolatile memories, disposed on the first surface of the substrate and between the two nonvolatile memories, and a plurality of terminals that are electrically connected to the two nonvolatile memories and to the controller, disposed on a second surface of the substrate.

Semiconductor module

In one embodiment, a preliminary solder layer made of a Sn alloy is formed on a connecting pad of a wiring substrate. A solder bump made of a Sn alloy is formed on an electrode pad of a semiconductor chip. After contacting the preliminary solder layer and the solder bump, the preliminary solder layer and the solder bump are melted by heating to a temperature of their melting points or higher to form a solder connecting part made of a Sn alloy containing Ag and Cu. Only the preliminary solder layer of the preliminary solder layer and the solder bump is composed of a Sn alloy containing Ag.

Semiconductor device and method for manufacturing the same

A semiconductor device is disclosed which comprises a plurality of semiconductor chips having a plurality of terminals, two chip mounting bases on each of which at least one of the semiconductor chips is mounted and a plurality of chip interconnections electrically connected to the terminals of the mounted semiconductor chip are formed into substantially the same pattern and which are stacked in two layers, one interconnection base which is interposed between the two chip mounting bases and on which a plurality of intermediate interconnections electrically connected to the chip interconnections are formed into a pattern different from the pattern of the chip interconnections, and a plurality of interlevel interconnections which are formed in a plurality of through holes extending through the chip mounting bases and the interconnection base at once along a stacking direction and electrically connect the chip interconnections and the intermediate interconnections.

Semiconductor device and manufacturing method therefor

There is disclosed a laminated-chip semiconductor device which comprises two chip-mounting substrates on each of which at least one semiconductor chip having a plurality of terminals for signals is mounted, and a plurality of chip connecting wirings electrically connected to the terminals for signals of the each semiconductor chip which are mounted on the chip-mounting substrates are formed in a same pattern, and which are laminated along a thickness direction, and one intermediate substrate which is arranged between the two chip-mounting substrates, and in which a plurality of interlayer connecting wirings electrically connected to each of the plurality of chip connecting wirings of the adjacent chip-mounting substrate are formed in a predetermined wiring pattern.

Laminated-chip semiconductor device

There is disclosed a semiconductor device which comprises a first chip-mounting substrate on which at least one semiconductor chip having a plurality of terminals is mounted, and a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, a second chip-mounting substrate which is laminated on the first chip-mounting substrate and on which at least one semiconductor chip is mounted, a plurality of relay terminals electrically connected to the respective terminals of the semiconductor chip are disposed to surround a portion with the semiconductor chip mounted thereon from the outside in the vicinity of the portion, and at least one of the semiconductor chips has a center offset from a center of a whole arrangement of the relay terminals.

Semiconductor device

An IC chip and overhang portions are stuck to tape by an adhesive agent layer having elasticity. A plurality of solder balls are attached to the tape. By soldering the solder balls to a printed board, a semiconductor device is mounted. In the case where a temperature cycle has been caused, thermal stress occurs between the IC chip and the printed board or between the hangover portion and the printed board because of a difference in coefficient of thermal expansion between the IC chip or the hangover portion and the printed board. However, this thermal stress is absorbed by the elasticity of the adhesive agent layer. As a result, little thermal stress is applied to solder balls. Even if the above described temperature cycle is repeated, therefore, the solder balls are electrically connected to the printed board stably over a long period of time. In addition, the area of the tape is widened by the area of the hangover portions. Accordingly, a larger number of solder balls can be attached to the tape without reducing the size of each of the solder balls.

Semiconductor device of surface mounting type and method for fabricating the same

In the disclosed method of manufacturing semiconductor devices with a single-sided resin-sealed package structure, when resin is filled into between the chip and the substrate, the occurrence of variations in the finishing dimensions of the package or defects in the outward appearance of the package is prevented. The disclosed manufacturing method comprises the step of using a guide plate for pouring resin and bringing one end of the guide plate into contact with one face end of a substrate or with a portion of one major surface near at least one side face of a chip in filling sealing resin between the chip and the substrate after the semiconductor chip has been mounted, with the face down, on one major surface of a wiring substrate having the wiring containing a connection section, the step of inclining the guide plate so that the guide plate may meet one major surface of the substrate at a specified angle, when or after one end of the guide plate is brought into contact with the substrate, and the step of supplying the resin to the opening between the chip and the substrate by supplying the resin onto the top surface of the guide plate and allowing the resin to flow over the top surface of the guide plate.

Method of manufacturing semiconductor devices

Growing community of inventors

Tokyo, Japan

Katsuhiko Oyama